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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_07.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity top is
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end entity top;
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architecture top_arch of top is
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  signal top_sig : -- . . .;                  -- 1
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    --
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    bit;
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    --
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begin
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  stimulus : process
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    is
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      variable var : -- . . .;                  -- 2
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      --
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      bit;
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    --
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  begin
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    -- . . .
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    --
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    report "--1: " & top'path_name;
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    report "--1: " & top'instance_name;
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    report "--1: " & top_sig'path_name;
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    report "--1: " & top_sig'instance_name;
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    report "--2: " & stimulus'path_name;
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    report "--2: " & stimulus'instance_name;
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    report "--2: " & var'path_name;
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    report "--2: " & var'instance_name;
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    wait;
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    --
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  end process stimulus;
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  rep_gen : for index in 0 to 7 generate
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  begin
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    end_gen : if index = 7 generate
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      signal end_sig : -- . . .;              -- 3
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        --
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        bit;
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        --
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    begin
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      -- . . .
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      assert false report "--3: " & end_sig'path_name;
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      assert false report "--3: " & end_sig'instance_name;
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      --
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    end generate end_gen;
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    other_gen : if index /= 7 generate
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      signal other_sig : -- . . .;            -- 4
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        --
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        bit;
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        --
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    begin
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      other_comp : entity work.bottom(bottom_arch)
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        port map ( -- . . . );
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          --
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          port_name => open );
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      assert false report "--4: " & other_sig'path_name;
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      assert false report "--4: " & other_sig'instance_name;
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      --
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    end generate other_gen;
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  end generate rep_gen;
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end architecture top_arch;
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