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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_ch_20_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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package ch_20_09_a is
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  attribute attr : integer;
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end package ch_20_09_a;
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use work.ch_20_09_a.all;
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entity e is
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  port ( p : in bit );
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  attribute attr of p : signal is 1;
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end entity e;
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architecture arch of e is
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begin
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  assert false report integer'image(p'attr);
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end architecture arch;
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use work.ch_20_09_a.all;
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entity ch_20_09 is
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end entity ch_20_09;
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architecture test of ch_20_09 is
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  signal s : bit;
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  attribute attr of s : signal is 2;
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begin
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  -- code from book
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  c1 : entity work.e(arch)
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    port map ( p => s );
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  -- end code from book
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end architecture test;
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