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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_19_tb-frk.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library qsim;
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library random;
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use std.textio.all;
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architecture fork of test_bench is
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  use qsim.qsim_types.all;
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  use random.random.all;
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  constant num_outputs : positive := 4;
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  constant probabilities : probability_vector(1 to num_outputs - 1)
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    := ( 0.2, 0.4, 0.1 );
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  signal source_arc : arc_type;
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  signal fork_arc : arc_vector(1 to num_outputs);
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  signal info_detail : info_detail_type := trace;
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begin
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  source1 : entity qsim.source(behavior)
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    generic map ( name => "source1",
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                  distribution => fixed,  mean_inter_arrival_time => 100 ns,
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                  seed => sample_seeds(1),
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                  time_unit => ns,
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                  info_file_name => "source1.dat" )
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    port map ( out_arc => source_arc,
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	       info_detail => info_detail );
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  fork1 : entity qsim.fork(behavior)
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    generic map ( name => "fork1",
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                  probabilities => probabilities,
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                  seed => sample_seeds(2),
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                  time_unit => ns,
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                  info_file_name => "fork1.dat" )
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    port map ( in_arc => source_arc,
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	       out_arc => fork_arc,
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               info_detail => info_detail );
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  source_monitor : process is
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                             variable L : line;
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  begin
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    wait on source_arc;
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    write(L, string'("source_monitor: at "));
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    write(L, now, unit => ns);
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    write(L, string'(", "));
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    write(L, source_arc.token, ns);
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    writeline(output, L);
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  end process source_monitor;
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  sinks : for index in 1 to num_outputs generate
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    constant index_string : string := integer'image(index);
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  begin
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    sink : entity qsim.sink(behavior)
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      generic map ( name => "sink" & index_string,
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                    time_unit => ns,
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                    info_file_name => "sink" & index_string & ".dat" )
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      port map ( in_arc => fork_arc(index),
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		 info_detail => info_detail );
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    sink_monitor : process
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      variable L : line;
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    begin
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      wait on fork_arc(index);
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      write(L, string'("sink_monitor(" & index_string & "): at "));
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      write(L, now, unit => ns);
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      write(L, string'(", "));
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      write(L, fork_arc(index).token, ns);
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      writeline(output, L);
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    end process sink_monitor;
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  end generate sinks;
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end architecture fork;
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