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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_18_fg_18_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_18_11 is
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end entity fg_18_11;
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architecture test of fg_18_11 is
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  subtype byte is bit_vector(7 downto 0);
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  type byte_array is array (natural range <>) of byte;
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  function resolve_bytes ( drivers : in byte_array ) return byte is
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  begin
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    return drivers(drivers'left);
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  end function resolve_bytes;
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  function resolve_bits ( drivers : in bit_vector ) return bit is
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  begin
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    return drivers(drivers'left);
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  end function resolve_bits;
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  -- code from book (in text)
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  signal address : bit_vector(15 downto 0);
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  signal data : resolve_bytes byte;
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  signal rd, wr, io : bit;    -- read, write, io/mem select
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  signal ready : resolve_bits bit;
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  -- end code from book
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begin
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-- code from book
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  bus_monitor : process is
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                          constant header : string(1 to 44)
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                        := FF & "      Time   R/W I/M  Address          Data";
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                        use std.textio.all;
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                        file log : text open write_mode is "buslog";
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                        variable trace_line : line;
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                        variable line_count : natural := 0;
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  begin
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    if line_count mod 60 = 0 then
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      write ( trace_line, header );
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      writeline ( log, trace_line );
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      writeline ( log, trace_line );    -- empty line
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    end if;
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    wait until (rd = '1' or wr = '1') and ready = '1';
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    write ( trace_line, now, justified => right, field => 10, unit => us );
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    write ( trace_line, string'("    ") );
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    if rd = '1' then
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      write ( trace_line, 'R' );
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    else
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      write ( trace_line, 'W' );
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    end if;
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    write ( trace_line, string'("   ") );
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    if io = '1' then
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      write ( trace_line, 'I' );
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    else
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      write ( trace_line, 'M' );
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    end if;
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    write ( trace_line, string'("   ") );
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    write ( trace_line, address );
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    write ( trace_line, ' ');
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    write ( trace_line, data );
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    writeline ( log, trace_line );
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    line_count := line_count + 1;
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  end process bus_monitor;
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-- end code from book
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  stimulus : process is
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  begin
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    wait for 0.4 us - now;
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    rd <= '1', '0' after 10 ns;
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    address <= X"0000";
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    data <= B"10011110";
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    ready <= '1', '0' after 10 ns;
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    wait for 0.9 us - now;
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    rd <= '1', '0' after 10 ns;
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    address <= X"0001";
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    data <= B"00010010";
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    ready <= '1', '0' after 10 ns;
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    wait for 2.0 us - now;
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    rd <= '1', '0' after 10 ns;
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    address <= X"0014";
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    data <= B"11100111";
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    ready <= '1', '0' after 10 ns;
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    wait for 2.7 us - now;
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    wr <= '1', '0' after 10 ns;
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    io <= '1', '0' after 10 ns;
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    address <= X"0007";
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    data <= X"00";
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    ready <= '1', '0' after 10 ns;
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    wait;
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  end process stimulus;
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end architecture test;
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