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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_18_ch_18_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_18_09 is
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end entity ch_18_09;
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----------------------------------------------------------------
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architecture test of ch_18_09 is
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begin
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  process is
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            use std.textio.all;
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          variable L : line;
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  begin
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    write(L, 42, justified => left, field => 5);
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    writeline(output, L);
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    write(L, 42, justified => right, field => 5);
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    writeline(output, L);
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    write(L, 123, field => 2);
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    writeline(output, L);
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    -- code from book:
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    write ( L, string'( "fred" ) );
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    write ( L, ' ' );
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    write ( L, bit_vector'( X"3A" ) );
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    -- end of code from book
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    writeline(output, L);
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    write(L, 3.14159, digits => 2);
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    writeline(output, L);
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    write(L, 123.4567, digits => 0);
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    writeline(output, L);
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    write(L, 40 ns, unit => ps);
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    writeline(output, L);
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    write(L, 23 us, unit => ms);
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    writeline(output, L);
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    wait;
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  end process;
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end architecture test;
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