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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity counter is
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  generic ( tipd_reset,                   -- input prop delay on reset
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            tipd_clk,                     -- input prop delay on clk
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            topd_q : delay_length;        -- output prop delay on q
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            tsetup_reset,                 -- setup: reset before clk
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            thold_reset : delay_length ); -- hold time: reset after clk
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  port ( reset,                           -- synchronous reset input
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         clk : in bit;                    -- edge triggered clock input
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         q : out bit_vector );            -- counter output
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end entity counter;
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