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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_ch_16_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity ch_16_02 is
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end entity ch_16_02;
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----------------------------------------------------------------
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architecture test of ch_16_02 is
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  -- code from book:
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  subtype word is bit_vector(0 to 31);
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  type word_array is array (integer range <>) of word;
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  function resolve_words ( words : word_array ) return word;
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  signal s : resolve_words word bus;
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  -- end of code from book
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  function resolve_words ( words : word_array ) return word is
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  begin
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    if words'length > 0 then
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      return words(words'left);
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    else
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      return X"00000000";
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    end if;
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  end function resolve_words;
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  constant T_delay : delay_length := 2 ns;
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begin
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  process is
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  begin
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    -- code from book (should fail)
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    s(0 to 15) <= X"003F" after T_delay;
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    s(16 to 31) <= null after T_delay;
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    -- end of code from book
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    wait;
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  end process;
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end architecture test;
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