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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_ch_16_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity ch_16_01 is
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end entity ch_16_01;
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----------------------------------------------------------------
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architecture test of ch_16_01 is
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  function pulled_up ( drivers : bit_vector ) return bit is
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  begin
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    for index in drivers'range loop
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      if drivers(index) = '0' then
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        return '0';
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      end if;
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    end loop;
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    return '1';
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  end function pulled_up;
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  type state_type is (init_state, state1, state2, state3);
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  type state_vector is array (integer range <>) of state_type;
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  function resolve_state ( drivers : state_vector ) return state_type is
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  begin
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    return drivers(drivers'left);
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  end function resolve_state;
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  -- code from book:
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  signal interrupt_request : pulled_up bit bus;
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  signal stored_state : resolve_state state_type register := init_state;
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  -- end of code from book
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begin
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end architecture test;
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