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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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use work.dlx_instr.all;
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architecture behavior of ir_extender is
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  subtype upper_6_bits is std_logic_vector(0 to 5);
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  subtype upper_16_bits is std_logic_vector(0 to 15);
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begin
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  extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
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  begin
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    if To_bit(immed_en) = '1' then
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      if To_bit(immed_size_26) = '1' then  -- 26-bit immediate
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      	if To_bit(immed_unsigned) = '1' then
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	  q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
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	else
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	  q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
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	end if;
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      else -- 16-bit immediate
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      	if To_bit(immed_unsigned) = '1' then
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	  q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
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	else
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	  q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
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	end if;
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      end if;
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    else
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      q <= disabled_dlx_word after Tpd;
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    end if;
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  end process extender;
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end architecture behavior;
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