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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_dlxtst-b.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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architecture bench of dlx_test is
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  use work.dlx_types.all;
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  component clock_gen is
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                        port ( phi1, phi2 : out std_logic;
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                               reset : out std_logic );
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  end component clock_gen;
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  component memory is
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                     port ( phi1, phi2 : in std_logic;
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                            a : in dlx_address;
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                            d : inout dlx_word;
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                            width : in dlx_mem_width;
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                            write_enable : in std_logic;
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                            burst : in std_logic := '0';
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                            mem_enable : in std_logic;
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                            ready : out std_logic );
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  end component memory;
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  component dlx is
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                  port ( phi1, phi2 : in std_logic;
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                         reset : in std_logic;
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                         halt : out std_logic;
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                         a : out dlx_address;
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                         d : inout dlx_word;
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                         width : out dlx_mem_width;
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                         write_enable : out std_logic;
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                         ifetch : out std_logic;
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                         mem_enable : out std_logic;
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                         ready : in std_logic );
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  end component dlx;
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  signal phi1, phi2, reset : std_logic;
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  signal a : dlx_address;
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  signal d : dlx_word;
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  signal halt : std_logic;
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  signal width : dlx_mem_width;
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  signal write_enable, mem_enable, ifetch, ready : std_logic;
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begin
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  cg : component clock_gen
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    port map ( phi1 => phi1, phi2 => phi2, reset => reset );
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  mem : component memory
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    port map ( phi1 => phi1, phi2 => phi2,
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               a => a, d => d,
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               width => width, write_enable => write_enable, burst => open,
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               mem_enable => mem_enable, ready => ready );
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  proc : component dlx
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    port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt,
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               a => a, d => d,
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               width => width, write_enable => write_enable, ifetch => ifetch,
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               mem_enable => mem_enable, ready => ready );
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end architecture bench;
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