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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_dlxt.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package dlx_types is
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  -- little-endian addresses
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  subtype dlx_address is std_logic_vector(31 downto 0);
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  subtype dlx_bv_address is bit_vector(31 downto 0);
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  -- big-endian data words
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  subtype dlx_word is std_logic_vector(0 to 31);
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  subtype dlx_bv_word is bit_vector(0 to 31);
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  type dlx_word_array is array (natural range <>) of dlx_word;
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  -- tristate bus driving value
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  constant disabled_dlx_word : dlx_word := ( others => 'Z' );
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  -- type for specifying data width on the data bus
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  subtype dlx_mem_width is std_logic_vector(1 downto 0);
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  constant dlx_mem_width_byte : dlx_mem_width := "01";
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  constant dlx_mem_width_halfword : dlx_mem_width := "10";
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  constant dlx_mem_width_word : dlx_mem_width := "00";
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  -- type for controlling trace information generated by model
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  type dlx_debug_control is
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    ( none,
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      msg_every_100_instructions, msg_each_instruction,
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      trace_each_instruction, trace_each_step );
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end package dlx_types;
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