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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_dlx.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               use work.dlx_types.all;
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               entity dlx is
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                 generic ( Tpd_clk_out : delay_length;
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                           debug : dlx_debug_control := none );
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                 port ( phi1, phi2 : in std_logic;
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                        reset : in std_logic;
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                        halt : out std_logic;
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                        a : out dlx_address;
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                        d : inout dlx_word;
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                        width : out dlx_mem_width;
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                        write_enable : out std_logic;
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                        ifetch : out std_logic;
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                        mem_enable : out std_logic;
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                        ready : in std_logic );
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               end entity dlx;
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