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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_04.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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library ieee;  use ieee.std_logic_1164.all;
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               entity DRAM is
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                 port ( a :  in std_logic_vector(0 to 10);
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                        d :  inout std_logic_vector(0 to 3);
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                        cs, we, ras, cas : in std_logic );
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               end entity DRAM;
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               architecture empty of DRAM is
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               begin
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                 d <= (others => 'Z');
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               end architecture empty;
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               library ieee;  use ieee.std_logic_1164.all;
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               entity memory_board is
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               end entity memory_board;
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-- end not in book
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               architecture chip_level of memory_board is
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                 component DRAM is
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                                  port ( a :  in std_logic_vector(0 to 10);
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                                         d :  inout std_logic_vector(0 to 3);
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                                         cs, we, ras, cas : in std_logic );
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                 end component DRAM;
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                 signal buffered_address : std_logic_vector(0 to 10);
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                 signal DRAM_data : std_logic_vector(0 to 31);
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                 signal bank_select : std_logic_vector(0 to 3);
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                 signal buffered_we, buffered_ras, buffered_cas : std_logic;
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                 -- . . .    -- other declarations
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               begin
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                 bank_array : for bank_index in 0 to 3 generate
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                 begin
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                   nibble_array : for nibble_index in 0 to 7 generate
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                     constant data_lo : natural := nibble_index * 4;
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                     constant data_hi : natural := nibble_index * 4 + 3;
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                   begin
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                     a_DRAM : component DRAM
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                       port map ( a => buffered_address,
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                                  d => DRAM_data(data_lo to data_hi),
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                                  cs => bank_select(bank_index),
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                                  we => buffered_we,
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                                  ras => buffered_ras,
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                                  cas => buffered_cas );
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                   end generate nibble_array;
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                 end generate bank_array;
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                 -- . . .    -- other component instances, etc
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                 -- not in book
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                 buffered_address <= "01010101010";
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                 DRAM_data <= X"01234567";
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                 -- end not in book
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               end architecture chip_level;
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