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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_21.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity reg is
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                 generic ( t_setup, t_hold, t_pd : delay_length;
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                           width : positive );
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                 port ( clock : in std_logic;
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                        reset_n : in std_logic;
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                        data_in : in std_logic_vector(0 to width - 1);
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                        data_out : out std_logic_vector(0 to width - 1) );
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               end entity reg;
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-- not in book
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               architecture gate_level of reg is
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               begin
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                 store : process (clock, reset_n) is
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                 begin
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                   if reset_n = '0' or reset_n = 'L' then
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                     data_out <= (others => '0') after t_pd;
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                   elsif rising_edge(clock) then
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                     data_out <= data_in after t_pd;
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                   end if;
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                 end process store;
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               end architecture gate_level;
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-- end not in book
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