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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package counter_types is
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  -- code from book (in text)
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  subtype digit is bit_vector(3 downto 0);
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  -- end code from book
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end package counter_types;
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use work.counter_types.digit;
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entity add_1 is
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  port ( d : in digit;  y : out digit );
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end entity add_1;
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architecture boolean_eqn of add_1 is
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begin
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  y(0) <= not d(0) after 4 ns;
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  y(1) <= (not d(1) and d(0))
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          or (d(1) and not d(0)) after 4 ns;
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  y(2) <= (not d(2) and d(1) and d(0))
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	  or (d(2) and not (d(1) and d(0))) after 4 ns;
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  y(3) <= (not d(3) and d(2) and d(1) and d(0))
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	  or (d(3) and not (d(2) and d(1) and d(0))) after 4 ns;
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end architecture boolean_eqn;
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use work.counter_types.digit;
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entity buf4 is
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  port ( a : in digit;  y : out digit );
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end entity buf4;
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architecture basic of buf4 is
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begin
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  y(0) <= a(0) after 2 ns;
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  y(1) <= a(1) after 2 ns;
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  y(2) <= a(2) after 2 ns;
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  y(3) <= a(3) after 2 ns;
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end architecture basic;
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-- code from book
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use work.counter_types.digit;
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entity counter is
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  port ( clk, clr : in bit;
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         q0, q1 : out digit );
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end entity counter;
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--------------------------------------------------
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architecture registered of counter is
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  component digit_register is
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                             port ( clk, clr : in bit;
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                                    d : in digit;
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                                    q : out digit );
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  end component digit_register;
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  signal current_val0, current_val1, next_val0, next_val1 : digit;
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begin
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  val0_reg : component digit_register
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    port map ( clk => clk, clr => clr, d => next_val0,
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               q => current_val0 );
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  val1_reg : component digit_register
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    port map ( clk => clk, clr => clr, d => next_val1,
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               q => current_val1 );
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  -- other component instances
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  -- . . .
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  -- not in book
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  incr0 : entity work.add_1(boolean_eqn)
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    port map ( d => current_val0, y => next_val0 );
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  incr1 : entity work.add_1(boolean_eqn)
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    port map ( d => current_val1, y => next_val1 );
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  buf0 : entity work.buf4(basic)
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    port map ( a => current_val0, y => q0 );
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  buf1 : entity work.buf4(basic)
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    port map ( a => current_val1, y => q1 );
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  -- end not in book
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end architecture registered;
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-- end code from book
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