Project

General

Profile

Download (2.88 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_12_fg_12_03.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
-- code from book
28

    
29
entity reg is
30
  generic ( width : positive );
31
  port ( d :  in  bit_vector(0 to width - 1);
32
         q :  out  bit_vector(0 to width - 1);
33
         clk, reset : in bit );
34
end entity reg;
35

    
36
--------------------------------------------------
37

    
38
architecture behavioral of reg is
39
begin
40

    
41
  behavior : process (clk, reset) is
42
                                    constant zero : bit_vector(0 to width - 1) := (others => '0');
43
  begin
44
    if reset = '1' then
45
      q <= zero;
46
    elsif clk'event and clk = '1' then
47
      q <= d;
48
    end if;
49
  end process behavior;
50

    
51
end architecture behavioral;
52

    
53
-- end code from book
54

    
55

    
56

    
57
entity fg_12_03 is
58
end entity fg_12_03;
59

    
60

    
61
architecture test of fg_12_03 is
62

    
63
  -- code from book
64

    
65
  subtype state_vector is bit_vector(1 to 5);
66

    
67
  -- end code from book
68

    
69
  signal clk, reset : bit := '0';
70
  signal word_in, word_out : bit_vector(0 to 31);
71
  signal state_in, state_out : state_vector;
72

    
73
begin
74

    
75
  -- code from book
76

    
77
  word_reg : entity work.reg(behavioral)
78
    generic map ( width => 32 )
79
    port map ( -- . . . );
80
      -- not in book
81
      d => word_in, q => word_out, clk => clk, reset => reset );
82
  -- end not in book
83

    
84
  state_reg : entity work.reg(behavioral)
85
    generic map ( width => state_vector'length )
86
    port map ( -- . . . );
87
      -- not in book
88
      d => state_in, q => state_out, clk => clk, reset => reset );
89

    
90
  -- end code from book
91

    
92
  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
93

    
94
  reset_gen : reset <= '1' after 80 ns, '0' after 105 ns;
95

    
96
  stimulus_word : word_in <= X"11111111" after 25 ns,
97
                             X"22222222" after 65 ns,
98
		             X"33333333" after 85 ns,
99
		             X"44444444" after 125 ns;
100

    
101
  stimulus_state : state_in <= "00001" after 25 ns,
102
                               "00010" after 65 ns,
103
		               "00011" after 85 ns,
104
		               "00100" after 125 ns;
105

    
106
end architecture test;
(190-190/267)