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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_12_fg_12_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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-- code from book
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entity control_unit is
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  generic ( Tpd_clk_out, Tpw_clk : delay_length;
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            debug : boolean := false );
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  port ( clk : in bit;
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         ready : in bit;
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         control1, control2 : out bit );
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end entity control_unit;
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-- end code from book
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architecture test of control_unit is
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begin
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end architecture test;
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entity fg_12_01 is
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end entity fg_12_01;
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architecture test of fg_12_01 is
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  signal clk, ready : bit;
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begin
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  dut1 : entity work.control_unit
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    -- code from book (in text)
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    generic map ( 200 ps, 1500 ps, false )
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    -- end code from book
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    port map ( clk, ready, open, open );
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  dut2 : entity work.control_unit
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    -- code from book (in text)
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    generic map ( Tpd_clk_out => 200 ps, Tpw_clk => 1500 ps )
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    -- end code from book
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    port map ( clk, ready, open, open );
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  dut3 : entity work.control_unit
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    -- code from book (in text)
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    generic map ( 200 ps, 1500 ps, debug => open )
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    -- end code from book
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    port map ( clk, ready, open, open );
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end architecture test;
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