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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_fg_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_11_01 is
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end entity fg_11_01;
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architecture test of fg_11_01 is
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  -- code from book (in text)
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  type tri_state_logic is ('0', '1', 'Z');
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  type tri_state_logic_array is array (integer range <>) of tri_state_logic;
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  -- end code from book
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  -- code from book
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  function resolve_tri_state_logic ( values : in tri_state_logic_array )
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    return tri_state_logic is
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    variable result : tri_state_logic := 'Z';
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  begin
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    for index in values'range loop
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      if values(index) /= 'Z' then
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        result := values(index);
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      end if;
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    end loop;
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    return result;
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  end function resolve_tri_state_logic;
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  -- end code from book
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  -- code from book (in text)
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  signal s1 : resolve_tri_state_logic tri_state_logic;
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  subtype resolved_logic is resolve_tri_state_logic tri_state_logic;
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  signal s2, s3 : resolved_logic;
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  -- end code from book
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begin
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  source_1 : s1 <= 'Z',
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                   '0' after 10 ns,
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                   'Z' after 20 ns,
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                   '1' after 30 ns,
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                   'Z' after 40 ns,
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	           '1' after 200 ns,
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	           'Z' after 220 ns;
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  source_2 : s1 <= 'Z',
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                   '0' after 110 ns,
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                   'Z' after 120 ns,
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                   '1' after 130 ns,
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                   'Z' after 140 ns,
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	           '1' after 200 ns,
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	           '0' after 210 ns,
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	           'Z' after 220 ns;
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end architecture test;
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