Project

General

Profile

Download (3.98 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_07_fg_07_22.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
-- not in book
28

    
29
entity cache is
30
end entity cache;
31

    
32
-- end not in book
33

    
34

    
35

    
36
architecture behavioral of cache is
37
  -- not in book
38
  subtype word is bit_vector(0 to 31);
39
  signal mem_addr : natural;
40
  signal mem_data_in : word;
41
  signal mem_read, mem_ack : bit := '0';
42
  -- end not in book
43
begin
44

    
45
  behavior : process is
46

    
47
                       -- not in book
48
                       constant block_size : positive := 4;
49
                     type cache_block is array (0 to block_size - 1) of word;
50
                     type store_array is array (0 to 15) of cache_block;
51
                     variable data_store : store_array;
52
                     variable entry_index : natural := 1;
53
                     variable miss_base_address : natural := 16;
54
                     -- end not in book
55

    
56
                     -- . . .
57

    
58
                     procedure read_block( start_address : natural;
59
                                           entry : out cache_block ) is
60

    
61
                       variable memory_address_reg : natural;
62
                       variable memory_data_reg : word;
63

    
64
                       procedure read_memory_word is
65
                       begin
66
                         mem_addr <= memory_address_reg;
67
                         mem_read <= '1';
68
                         wait until mem_ack = '1';
69
                         memory_data_reg := mem_data_in;
70
                         mem_read <= '0';
71
                         wait until mem_ack = '0';
72
                       end procedure read_memory_word;
73

    
74
                     begin  -- read_block
75
                       for offset in 0 to block_size - 1 loop
76
                         memory_address_reg := start_address + offset;
77
                         read_memory_word;
78
                         entry(offset) := memory_data_reg;
79
                       end loop;
80
                     end procedure read_block;
81

    
82
  begin  -- behavior
83
    -- . . .
84
    read_block( miss_base_address, data_store(entry_index) );
85
    -- . . .
86
    -- not in book
87
    wait;
88
    -- end not in book
89
  end process behavior;
90

    
91

    
92
  -- not in book
93

    
94
  memory : process is
95

    
96
                     type store_array is array (0 to 31) of word;
97
                   constant store : store_array :=
98
                     ( X"00000000", X"00000001", X"00000002", X"00000003",
99
                       X"00000004", X"00000005", X"00000006", X"00000007",
100
                       X"00000008", X"00000009", X"0000000a", X"0000000b",
101
                       X"0000000c", X"0000000d", X"0000000e", X"0000000f",
102
                       X"00000010", X"00000011", X"00000012", X"00000013",
103
                       X"00000014", X"00000015", X"00000016", X"00000017",
104
                       X"00000018", X"00000019", X"0000001a", X"0000001b",
105
                       X"0000001c", X"0000001d", X"0000001e", X"0000001f" );
106

    
107
  begin
108
    wait until mem_read = '1';
109
    mem_data_in <= store(mem_addr);
110
    mem_ack <= '1';
111
    wait until mem_read = '0';
112
    mem_ack <= '0';
113
  end process memory;
114

    
115
  -- end not in book
116

    
117

    
118
end architecture behavioral;
(158-158/267)