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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_19.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_19 is
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end entity fg_07_19;
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architecture test of fg_07_19 is
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  constant Thold_d_clk : delay_length := 3 ns;
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  signal clk, d : bit := '0';
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begin
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  -- code from book
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  hold_time_checker : process ( clk, d ) is
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                                           variable last_clk_edge_time : time := 0 fs;
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  begin
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    if clk'event and clk = '1' then
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      last_clk_edge_time := now;
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    end if;
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    if d'event then
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      assert now - last_clk_edge_time >= Thold_d_clk
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        report "hold time violation";
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    end if;
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  end process hold_time_checker;
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  -- end code from book
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  clk_gen : clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
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  stimulus : d <= '1' after 15 ns,
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                  '0' after 53 ns,
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                  '1' after 72 ns;
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end architecture test;
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