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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_17.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_17 is
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end entity fg_07_17;
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architecture test of fg_07_17 is
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  -- code from book
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  function bv_to_natural ( bv : in bit_vector ) return natural is
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    variable result : natural := 0;
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  begin
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    for index in bv'range loop
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      result := result * 2 + bit'pos(bv(index));
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    end loop;
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    return result;
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  end function bv_to_natural;
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  -- end code from book
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  signal data : bit_vector(0 to 7);
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  constant address : bit_vector(0 to 3) := "0101";
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  constant Taccess : delay_length := 80 ns;
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begin
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  tester : process is
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                     constant rom_size : natural := 8;
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                   constant word_size : natural := 8;
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                   -- code from book (in text)
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                   type rom_array is array (natural range 0 to rom_size-1)
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                     of bit_vector(0 to word_size-1);
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                   variable rom_data : rom_array;
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                   -- end code from book
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  begin
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    rom_data := (X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07");
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    -- code from book (in text)
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    data <= rom_data ( bv_to_natural(address) ) after Taccess;
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    -- end code from book
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    wait;
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  end process tester;
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end architecture test;
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