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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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entity signal_generator is
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  generic ( period : delay_length := 20 ns;
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            pulse_count : natural := 5 );
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end entity signal_generator;
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-- end not in book
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library ieee;  use ieee.std_logic_1164.all;
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architecture top_level of signal_generator is
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  signal raw_signal : std_ulogic;
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  -- . . .
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  procedure generate_pulse_train ( width, separation : in delay_length;
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                                   number : in natural;
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                                   signal s : out std_ulogic ) is
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  begin
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    for count in 1 to number loop
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      s <= '1', '0' after width;
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      wait for width + separation;
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    end loop;
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  end procedure generate_pulse_train;
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begin
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  raw_signal_generator : process is
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  begin
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    -- . . .
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    generate_pulse_train ( width => period / 2,
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                           separation => period - period / 2,
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                           number => pulse_count,
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                           s => raw_signal );
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    -- . . .
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    -- not in book
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    wait;
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    -- end not in book
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  end process raw_signal_generator;
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  -- . . .
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end architecture top_level;
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