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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_08.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_08 is
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end entity fg_07_08;
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architecture test of fg_07_08 is
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  subtype word32 is bit_vector(31 downto 0);
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  -- code in book
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  procedure negate ( a : inout word32 ) is
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    variable carry_in : bit := '1';
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    variable carry_out : bit;
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  begin
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    a := not a;
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    for index in a'reverse_range loop
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      carry_out :=  a(index) and carry_in;
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      a(index) := a(index) xor carry_in;
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      carry_in := carry_out;
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    end loop;
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  end procedure negate;
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  -- end code in book
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begin
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  stimulus : process is
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                       -- code in book (in text)
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                       variable op1 : word32;
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                     -- . . .
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                     -- end code in book
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  begin
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    op1 := X"0000_0002";
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    -- code in book (in text)
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    negate ( op1 );
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    -- end code in book
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    wait;
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  end process stimulus;
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end architecture test;
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