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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture behavioral of product_adder_subtracter is
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begin
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  behavior : process (a, b) is
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                              constant Tpd_in_out : time := 3 ns;
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                            variable op2 : std_ulogic_vector(b'range);
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                            variable carry_in : std_ulogic;
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                            variable carry_out : std_ulogic;
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  begin
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    carry_out := To_X01(mode);
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    if To_X01(mode) = '1' then
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      op2 := not b;
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    else
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      op2 := b;
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    end if;
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    for index in 0 to 31 loop
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      carry_in := carry_out;  -- of previous bit
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      s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
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      carry_out := (a(index) and op2(index))
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      	      	   or (carry_in and (a(index) xor op2(index)));
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    end loop;
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    s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
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  end process behavior;
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end architecture behavioral;
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