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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_06_mac-r.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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architecture rtl of mac is
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  signal pipelined_x_real,
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    pipelined_x_imag,
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    pipelined_y_real, 
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    pipelined_y_imag : std_ulogic_vector(15 downto 0);
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  signal real_part_product_1, 
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    real_part_product_2,
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    imag_part_product_1, 
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    imag_part_product_2 : std_ulogic_vector(31 downto 0);
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  signal pipelined_real_part_product_1,
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    pipelined_real_part_product_2,
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    pipelined_imag_part_product_1,
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    pipelined_imag_part_product_2 : std_ulogic_vector(31 downto 0);
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  signal real_product, 
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    imag_product : std_ulogic_vector(32 downto 0);
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  signal pipelined_real_product,
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    pipelined_imag_product : std_ulogic_vector(19 downto 0);
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  signal real_sum,
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    imag_sum : std_ulogic_vector(21 downto 0);
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  signal real_accumulator_ovf,
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    imag_accumulator_ovf : std_ulogic;
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  signal pipelined_real_sum,
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    pipelined_imag_sum : std_ulogic_vector(21 downto 0);
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  signal pipelined_real_accumulator_ovf,
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    pipelined_imag_accumulator_ovf : std_ulogic;
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begin
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  x_real_input_reg : entity work.reg(behavioral)
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    port map ( clk => clk, d => x_real, q => pipelined_x_real );
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  x_imag_input_reg : entity work.reg(behavioral)
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    port map ( clk => clk, d => x_imag, q => pipelined_x_imag );
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  y_real_input_reg : entity work.reg(behavioral)
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    port map ( clk => clk, d => y_real, q => pipelined_y_real );
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  y_imag_input_reg : entity work.reg(behavioral)
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    port map ( clk => clk, d => y_imag, q => pipelined_y_imag );
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  real_mult_1 : entity work.multiplier(behavioral)
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    port map ( a => pipelined_x_real, b => pipelined_y_real,
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	       p => real_part_product_1 );
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  real_mult_2 : entity work.multiplier(behavioral)
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    port map ( a => pipelined_x_imag, b => pipelined_y_imag,
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	       p => real_part_product_2 );
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  imag_mult_1 : entity work.multiplier(behavioral)
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    port map ( a => pipelined_x_real, b => pipelined_y_imag,
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	       p => imag_part_product_1 );
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  imag_mult_2 : entity work.multiplier(behavioral)
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    port map ( a => pipelined_x_imag, b => pipelined_y_real,
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	       p => imag_part_product_2 );
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  real_part_product_reg_1 : entity work.reg(behavioral)
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    port map ( clk => clk, d => real_part_product_1,
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	       q => pipelined_real_part_product_1 );
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  real_part_product_reg_2 : entity work.reg(behavioral)
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    port map ( clk => clk, d => real_part_product_2,
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	       q => pipelined_real_part_product_2 );
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  imag_part_product_reg_1 : entity work.reg(behavioral)
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    port map ( clk => clk, d => imag_part_product_1,
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	       q => pipelined_imag_part_product_1 );
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  imag_part_product_reg_2 : entity work.reg(behavioral)
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    port map ( clk => clk, d => imag_part_product_2,
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	       q => pipelined_imag_part_product_2 );
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  real_product_subtracter : entity work.product_adder_subtracter(behavioral)
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    port map ( mode => '1',
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               a => pipelined_real_part_product_1,
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	       b => pipelined_real_part_product_2,
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	       s => real_product );
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  imag_product_adder : entity work.product_adder_subtracter(behavioral)
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    port map ( mode => '0',
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               a => pipelined_imag_part_product_1,
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	       b => pipelined_imag_part_product_2,
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	       s => imag_product );
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  real_product_reg : entity work.reg(behavioral)
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    port map ( clk => clk,
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	       d => real_product(32 downto 13),
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	       q => pipelined_real_product );
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  imag_product_reg : entity work.reg(behavioral)
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    port map ( clk => clk,
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	       d => imag_product(32 downto 13),
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	       q => pipelined_imag_product );
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  real_accumulator : entity work.accumulator_adder(behavioral)
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    port map ( a(19 downto 0) => pipelined_real_product(19 downto 0),
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	       a(20) => pipelined_real_product(19),
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	       a(21) => pipelined_real_product(19),
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	       b => pipelined_real_sum,
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	       s => real_sum,
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	       ovf => real_accumulator_ovf );
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  imag_accumulator : entity work.accumulator_adder(behavioral)
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    port map ( a(19 downto 0) => pipelined_imag_product(19 downto 0),
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	       a(20) => pipelined_imag_product(19),
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	       a(21) => pipelined_imag_product(19),
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	       b => pipelined_imag_sum,
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	       s => imag_sum,
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	       ovf => imag_accumulator_ovf );
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  real_accumulator_reg : entity work.accumulator_reg(behavioral)
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    port map ( clk => clk, clr => clr,
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	       d => real_sum,  q => pipelined_real_sum );
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  imag_accumulator_reg : entity work.accumulator_reg(behavioral)
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    port map ( clk => clk, clr => clr,
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	       d => imag_sum,  q => pipelined_imag_sum );
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  real_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
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    port map ( clk => clk,
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               set => real_accumulator_ovf, clr => clr,
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	       q => pipelined_real_accumulator_ovf );
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  imag_accumulator_ovf_reg : entity work.synch_sr_ff(behavioral)
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    port map ( clk => clk,
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               set => imag_accumulator_ovf, clr => clr,
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	       q => pipelined_imag_accumulator_ovf );
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  s_real <= pipelined_real_sum(21) & pipelined_real_sum(16 downto 2);
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  s_imag <= pipelined_imag_sum(21) & pipelined_imag_sum(16 downto 2);
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  result_overflow_logic : entity work.overflow_logic(behavioral)
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    port map ( real_accumulator_ovf => pipelined_real_accumulator_ovf,
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	       imag_accumulator_ovf => pipelined_imag_accumulator_ovf,
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	       real_sum => pipelined_real_sum(21 downto 17),
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	       imag_sum => pipelined_imag_sum(21 downto 17),
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	       ovf => ovf );
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end architecture rtl;
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