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 Copyright (C) 1996 Morgan Kaufmann Publishers, Inc

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 This file is part of VESTs (Vhdl tESTs).

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 VESTs is free software; you can redistribute it and/or modify it

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 under the terms of the GNU General Public License as published by the

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 Free Software Foundation; either version 2 of the License, or (at

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 your option) any later version.

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 VESTs is distributed in the hope that it will be useful, but WITHOUT

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 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

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 for more details.

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 You should have received a copy of the GNU General Public License

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 along with VESTs; if not, write to the Free Software Foundation,

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 Inc., 59 Temple Place, Suite 330, Boston, MA 021111307 USA

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 $Id: ch_06_macb.vhd,v 1.2 20011026 16:29:34 paw Exp $

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 $Revision: 1.2 $

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architecture behavioral of mac is

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constant Tpd_clk_out : time := 3 ns;

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signal fp_x_real, fp_x_imag,

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fp_y_real, fp_y_imag,

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fp_s_real, fp_s_imag : real := 0.0;

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begin

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x_real_converter : entity work.to_fp(behavioral)

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port map ( x_real, fp_x_real );

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x_imag_converter : entity work.to_fp(behavioral)

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port map ( x_imag, fp_x_imag );

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y_real_converter : entity work.to_fp(behavioral)

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port map ( y_real, fp_y_real );

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y_imag_converter : entity work.to_fp(behavioral)

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port map ( y_imag, fp_y_imag );

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behavior : process (clk) is

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variable input_x_real, input_x_imag, input_y_real, input_y_imag : real := 0.0;

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variable real_part_product_1, real_part_product_2,

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imag_part_product_1, imag_part_product_2 : real := 0.0;

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variable real_product, imag_product : real := 0.0;

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variable real_sum, imag_sum : real := 0.0;

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variable real_accumulator_ovf, imag_accumulator_ovf : boolean := false;

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type boolean_to_stdulogic_table is array (boolean) of std_ulogic;

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constant boolean_to_stdulogic : boolean_to_stdulogic_table

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:= (false => '0', true => '1');

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begin

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if rising_edge(clk) then

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 work from the end of the pipeline back to the start, so as

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 not to overwrite previous results in pipeline registers before

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 they are used

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 update accumulator and generate outputs

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if To_X01(clr) = '1' then

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real_sum := 0.0;

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real_accumulator_ovf := false;

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imag_sum := 0.0;

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imag_accumulator_ovf := false;

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else

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real_sum := real_product + real_sum;

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real_accumulator_ovf := real_accumulator_ovf

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or real_sum < 16.0 or real_sum >= +16.0;

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imag_sum := imag_product + imag_sum;

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imag_accumulator_ovf := imag_accumulator_ovf

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or imag_sum < 16.0 or imag_sum >= +16.0;

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end if;

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fp_s_real <= real_sum after Tpd_clk_out;

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fp_s_imag <= imag_sum after Tpd_clk_out;

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ovf <= boolean_to_stdulogic(

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real_accumulator_ovf or imag_accumulator_ovf

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or real_sum < 1.0 or real_sum >= +1.0

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or imag_sum < 1.0 or imag_sum >= +1.0 )

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after Tpd_clk_out;

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 update product registers using partial products

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real_product := real_part_product_1  real_part_product_2;

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imag_product := imag_part_product_1 + imag_part_product_2;

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 update partial product registers using latched inputs

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real_part_product_1 := input_x_real * input_y_real;

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real_part_product_2 := input_x_imag * input_y_imag;

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imag_part_product_1 := input_x_real * input_y_imag;

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imag_part_product_2 := input_x_imag * input_y_real;

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 update input registers using MAC inputs

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input_x_real := fp_x_real;

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input_x_imag := fp_x_imag;

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input_y_real := fp_y_real;

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input_y_imag := fp_y_imag;

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end if;

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end process behavior;

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s_real_converter : entity work.to_vector(behavioral)

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port map ( fp_s_real, s_real );

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s_imag_converter : entity work.to_vector(behavioral)

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port map ( fp_s_imag, s_imag );

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end architecture behavioral;
