Project

General

Profile

Download (1.65 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_05_fg_05_30.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
23
-- $Revision: 1.1.1.1 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
library widget_cells, wasp_lib;
28

    
29
architecture cell_based of filter is
30

    
31
  -- declaration of signals, etc
32
  -- . . .
33

    
34
  -- not in book
35

    
36
  signal clk, filter_clk, accum_en, carry : bit;
37
  signal sum, alu_op1, alu_op2, result : bit_vector(31 downto 0);
38

    
39
  -- end not in book
40

    
41
begin
42

    
43
  clk_pad : entity wasp_lib.in_pad
44
    port map ( i => clk, z => filter_clk );
45

    
46
  accum : entity widget_cells.reg32
47
    port map ( en => accum_en, clk => filter_clk, d => sum,
48
               q => result );
49

    
50
  alu : entity work.adder
51
    port map ( a => alu_op1, b => alu_op2, y => sum, c => carry );
52

    
53
  -- other component instantiations
54
  -- . . .
55

    
56
end architecture cell_based;
(99-99/267)