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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_28.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity reg is
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  port ( d : in bit_vector(7 downto 0);
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         q : out bit_vector(7 downto 0);
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         clk : in bit );
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end entity reg;
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--------------------------------------------------
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-- not in book
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entity microprocessor is
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end entity microprocessor;
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-- end not in book
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architecture RTL of microprocessor is
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  signal interrupt_req : bit;
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  signal interrupt_level : bit_vector(2 downto 0);
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  signal carry_flag, negative_flag, overflow_flag, zero_flag : bit;
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  signal program_status : bit_vector(7 downto 0);
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  signal clk_PSR : bit;
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  -- . . .
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begin
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  PSR : entity work.reg
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    port map ( d(7) => interrupt_req,
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               d(6 downto 4) => interrupt_level,
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               d(3) => carry_flag,     d(2) => negative_flag,
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               d(1) => overflow_flag,  d(0) => zero_flag,
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               q => program_status,
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               clk => clk_PSR );
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  -- . . .
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end architecture RTL;
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