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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_16.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity and2 is
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                 port ( a, b : in std_ulogic;  y : out std_ulogic );
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               end entity and2;
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--------------------------------------------------
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               architecture detailed_delay of and2 is
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                 signal result : std_ulogic;
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               begin
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                 gate : process (a, b) is
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                 begin
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                   result <= a and b;
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                 end process gate;
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                 delay : process (result) is
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                 begin
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                   if result = '1' then
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                     y <= reject 400 ps inertial '1' after 1.5 ns;
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                   elsif result = '0' then
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                     y <= reject 300 ps inertial '0' after 1.2 ns;
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                   else
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                     y <= reject 300 ps inertial 'X' after 500 ps;
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                   end if;
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                 end process delay;
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               end architecture detailed_delay;
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