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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_02.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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architecture primitive of and_or_inv is
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  signal and_a, and_b : bit;
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  signal or_a_b : bit;
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begin
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  and_gate_a : process (a1, a2) is
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  begin
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    and_a <= a1 and a2;
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  end process and_gate_a;
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  and_gate_b : process (b1, b2) is
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  begin
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    and_b <= b1 and b2;
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  end process and_gate_b;
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  or_gate : process (and_a, and_b) is
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  begin
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    or_a_b <= and_a or and_b;
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  end process or_gate;
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  inv : process (or_a_b) is
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  begin
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    y <= not or_a_b;
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  end process inv;
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end architecture primitive;
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