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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_01.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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library ieee;  use ieee.std_logic_1164.all;
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-- end not in book
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               entity program_ROM is
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                 port ( address : in std_ulogic_vector(14 downto 0);
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                        data : out std_ulogic_vector(7 downto 0);
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                        enable : in std_ulogic );
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                 subtype instruction_byte is bit_vector(7 downto 0);
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                 type program_array is array (0 to 2**14 - 1) of instruction_byte;
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                 constant program : program_array
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                   := ( X"32", X"3F", X"03",  -- LDA  $3F03
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                        X"71", X"23",         -- BLT    $23
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                        -- not in book
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                        others => X"00"
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                        -- end not in book
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                        -- . . .
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                        );
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               end entity program_ROM;
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