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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_26.vhd,v 1.2 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_26 is
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end entity ch_05_26;
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-- code from book:
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library widget_cells, wasp_lib;
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use widget_cells.reg32;
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-- end of code from book
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architecture test of ch_05_26 is
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  signal filter_clk, accum_en : bit;
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  signal sum, result : bit_vector(31 downto 0);
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begin
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  -- code from book:
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  accum : entity reg32
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    port map ( en => accum_en, clk => filter_clk, d => sum,
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               q => result );
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  -- end of code from book
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end architecture test;
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