Project

General

Profile

Download (1.84 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_04_ch_04_08.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
entity ch_04_08 is
28

    
29
end entity ch_04_08;
30

    
31

    
32
----------------------------------------------------------------
33

    
34

    
35
architecture test of ch_04_08 is
36
begin
37

    
38

    
39
  process_04_3_b : process is
40

    
41
                             -- code from book:
42

    
43
                             type array1 is array (1 to 100) of integer;
44
                           type array2 is array (100 downto 1) of integer;
45

    
46
                           variable a1 : array1;
47
                           variable a2 : array2;
48

    
49
                           -- end of code from book
50

    
51
  begin
52

    
53
    a1(11 to 20) := a1(11 to 20);
54
    a2(50 downto 41) := a2(50 downto 41);
55

    
56
    a1(10 to 1) := a1(10 to 1);
57
    a2(1 downto 10) := a2(1 downto 10);
58

    
59
    a1(10 downto 1) := a1(10 downto 1);  -- illegal
60
    a2(1 to 10) := a2(1 to 10);  -- illegal;
61

    
62
    wait;
63
  end process process_04_3_b;
64

    
65

    
66
end architecture test;
(59-59/267)