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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_ch_04_07.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_04_07 is
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end entity ch_04_07;
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----------------------------------------------------------------
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architecture test of ch_04_07 is
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begin
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  process_04_3_a : process is
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                             -- code from book:
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                             subtype pixel_row is bit_vector (0 to 15);
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                           variable current_row, mask : pixel_row;
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                           -- end of code from book
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  begin
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    current_row := "0000000011111111";
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    mask := "0000111111110000";
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    -- code from book:
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    current_row := current_row and not mask;
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    current_row := current_row xor X"FFFF";
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    -- end of code from book
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    -- code from book (conditions only):
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    assert B"10001010" sll 3  =  B"01010000";
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    assert B"10001010" sll -2  =  B"00100010";
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    assert B"10010111" srl 2  = B"00100101";
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    assert B"10010111" srl -6  =  B"11000000";
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    assert B"01001011" sra 3  =  B"00001001";
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    assert B"10010111" sra 3  =  B"11110010";
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    assert B"00001100" sla 2  =  B"00110000";
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    assert B"00010001" sla 2  =  B"01000111";
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    assert B"00010001" sra -2  =  B"01000111";
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    assert B"00110000" sla -2  =  B"00001100";
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    assert B"10010011" rol 1  =  B"00100111";
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    assert B"10010011" ror 1  =  B"11001001";
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    assert "abc" & 'd'  =  "abcd";
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    assert 'w' & "xyz"  =  "wxyz";
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    assert 'a' & 'b'  =  "ab";
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    -- end of code from book
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    wait;
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  end process process_04_3_a;
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end architecture test;
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