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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_ch_04_06.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_04_06 is
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end entity ch_04_06;
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----------------------------------------------------------------
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--library ieee;  use ieee.std_logic_1164.std_ulogic;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of ch_04_06 is
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  -- code from book:
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  type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
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  --
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  subtype std_ulogic_word is std_ulogic_vector(0 to 31);
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  --
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  signal csr_offset : std_ulogic_vector(2 downto 1);
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  -- end of code from book
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begin
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  process_04_2_b : process is
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                             -- code from book:
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                             type string is array (positive range <>) of character;
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                           --
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                           constant LCD_display_len : positive := 20;
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                           subtype LCD_display_string is string(1 to LCD_display_len);
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                           variable LCD_display : LCD_display_string := (others => ' ');
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                           --
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                           type bit_vector is array (natural range <>) of bit;
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                           --
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                           subtype byte is bit_vector(7 downto 0);
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                           --
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                           variable channel_busy_register : bit_vector(1 to 4);
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                           --
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                           constant ready_message  : string := "Ready     ";
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                           --
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                           variable current_test : std_ulogic_vector(0 to 13) := "ZZZZZZZZZZ----";
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                           --
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                           constant all_ones : std_ulogic_vector(15 downto 0) := X"FFFF";
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                           -- end of code from book
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  begin
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    -- code from book:
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    channel_busy_register := b"0000";
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    -- end of code from book
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    wait;
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  end process process_04_2_b;
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end architecture test;
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