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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_ch_04_04.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_04_04 is
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end entity ch_04_04;
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----------------------------------------------------------------
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architecture test of ch_04_04 is
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begin
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  process_04_1_i : process is
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                             -- code from book:
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                             type A is array (1 to 4, 31 downto 0) of boolean;
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                           -- end of code from book
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                           variable free_map : bit_vector(1 to 10) := "0011010110";
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                           variable count : natural;
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  begin
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    -- code from book (just the conditions):
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    assert A'left(1) = 1;      assert A'low(1) = 1;
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    assert A'right(2) = 0 ;    assert A'high(2) = 31;
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    assert A'length(1) = 4;    assert A'length(2) = 32;
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    assert A'ascending(1) = true;    assert A'ascending(2) = false;
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    assert A'low = 1;    assert A'length = 4;
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    --
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    count := 0;
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    for index in free_map'range loop
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      if free_map(index) = '1' then
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        count := count + 1;
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      end if;
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    end loop;
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    -- end of code from book
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    wait;
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  end process process_04_1_i;
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end architecture test;
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