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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_fg_03_09.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity edge_triggered_register is
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  port ( clock : in bit; 
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         d_in : in real;  d_out : out real );
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end entity edge_triggered_register;
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architecture check_timing of edge_triggered_register is
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begin
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  store_and_check : process (clock) is
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                                      variable stored_value : real;
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                                    variable pulse_start : time;
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  begin
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    case clock is
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      when '1' =>
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        pulse_start := now;
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        stored_value := d_in;
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        d_out <= stored_value;
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      when '0' =>
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        assert now = 0 ns or (now - pulse_start) >= 5 ns
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          report "clock pulse too short"; 
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    end case;
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  end process store_and_check;
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end architecture check_timing;
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