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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_18.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_18 is
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end entity ch_03_18;
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architecture test of ch_03_18 is
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begin
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  process_3_5_a : process is
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                            constant initial_value : natural := 10;
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                          constant max_value : natural := 8;
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                          constant current_character : character := 'A';
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                          constant input_string : string := "012ABC";
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                          constant free_memory : natural := 0;
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                          constant low_water_limit : natural := 1024;
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                          constant packet_length : natural := 0;
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                          constant clock_pulse_width : delay_length := 10 ns;
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                          constant min_clock_width : delay_length := 20 ns;
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                          constant last_position : natural := 10;
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                          constant first_position : natural := 5;
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                          constant number_of_entries : natural := 0;
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  begin
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    -- code from book:
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    assert initial_value <= max_value;
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    --
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    assert initial_value <= max_value
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                            report "initial value too large";
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    --
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    assert current_character >= '0' and current_character <= '9'
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                                                             report "Input number " & input_string & " contains a non-digit";
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    --
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    assert free_memory >= low_water_limit
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      report "low on memory, about to start garbage collect"
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      severity note;
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    --
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    assert packet_length /= 0
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      report "empty network packet received"
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      severity warning;
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    --
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    assert clock_pulse_width >= min_clock_width
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      severity error;
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    --
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    assert (last_position - first_position + 1) = number_of_entries
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      report "inconsistency in buffer model"
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      severity failure;
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    -- end of code from book
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    wait;
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  end process process_3_5_a;
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end architecture test;
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