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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_07 is
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end entity ch_03_07;
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architecture test of ch_03_07 is
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begin
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  process_03_2_b : process is
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                             -- code from book:
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                             subtype index_mode is integer range 0 to 3;
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                           variable instruction_register : integer range 0 to 2**16 - 1;
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                           -- end of code from book
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                           variable index_value : integer;
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                           constant accumulator_A : integer := 1;
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                           constant accumulator_B : integer := 2;
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                           constant index_register : integer := 3;
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  begin
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    for i in index_mode loop
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      instruction_register := i * 2**12;
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      -- code from book:
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      case index_mode'((instruction_register / 2**12) rem 2**2) is
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        when 0 =>
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          index_value := 0;
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        when 1 =>
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          index_value := accumulator_A;
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        when 2 =>
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          index_value := accumulator_B;
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        when 3 =>
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          index_value := index_register;
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      end case;
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      -- end of code from book
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    end loop;
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    wait;
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  end process process_03_2_b;
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end architecture test;
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