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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_03_ch_03_04.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_03_04 is
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end entity ch_03_04;
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architecture test of ch_03_04 is
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  type opcode_type is (opcode_1, opcode_2, halt_opcode);
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  signal opcode : opcode_type := opcode_1;
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  signal halt_indicator : boolean := false;
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begin
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  process_3_1_d : process (opcode) is
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                                     variable PC : integer := 0;
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                                   constant effective_address : integer := 1;
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                                   variable executing : boolean := true;
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  begin
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    -- code from book:
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    if opcode = halt_opcode then
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      PC := effective_address;
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      executing := false;
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      halt_indicator <= true;
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    end if;
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    -- end of code from book
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  end process process_3_1_d;
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  stimulus : process is
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  begin
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    opcode <= opcode_2 after 100 ns, halt_opcode after 200 ns;
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    wait;
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  end process stimulus;
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end architecture test;
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