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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_fg_a_06.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity fg_a_06 is
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end entity fg_a_06;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of fg_a_06 is
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  -- code from book
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  constant terminal_count : integer := 2**6 - 1;
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  subtype counter_range is integer range 0 to terminal_count;
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  signal count : counter_range;
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  -- . . .
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  -- end code from book
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  signal clk, reset : std_ulogic;
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begin
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  -- code from book
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  counter6 : process (reset, clk)
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  begin
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    if reset = '0' then
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      count <= 0;
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    elsif rising_edge(clk) then
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      if count < terminal_count then
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        count <= count + 1;
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      else
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        count <= 0;
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      end if;
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    end if;
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  end process counter6;
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  -- end code from book
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  stimulus : process is
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  begin
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    reset <= '1';  clk <= '0';  wait for 10 ns;
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    clk <= '1', '0' after 10 ns;  wait for 20 ns;
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    clk <= '1', '0' after 10 ns;  wait for 20 ns;
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    clk <= '1', '0' after 10 ns;  wait for 20 ns;
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    reset <= '0', '1' after 30 ns;
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    clk <= '1' after 10 ns, '0' after 20 ns;
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    wait for 40 ns;
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    for i in 1 to terminal_count + 10 loop
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      clk <= '1', '0' after 10 ns;
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      wait for 20 ns;
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    end loop;
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    wait;
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  end process stimulus;
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end architecture test;
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