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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_ap_a_01.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ap_a_01 is
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end entity ap_a_01;
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library ieee;  use ieee.std_logic_1164.all;
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architecture test of ap_a_01 is
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  signal clk : std_ulogic;
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begin
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  process (clk) is
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                  -- code from book
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                  -- end code from book
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  begin
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    if
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      -- code from book
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      clk'event and (To_X01(clk) = '1') and (To_X01(clk'last_value) = '0')
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      -- end code from book
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    then
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      report "rising edge on clk";
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    end if;
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  end process;
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  clk <= '0', '1' after 10 ns, '0' after 20 ns,
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         '1' after 30 ns, '0' after 40 ns;
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end architecture test;
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