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-------------------------------------------------------------------------------
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--| @file timer.vhd
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--| @brief General Purpose Timer. It is of customizable length,
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--|        the minimum being 4-bits, one for the actual timing, the other
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--|        three for control. (timer.vhd, original file name)
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--|
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--| @author         Richard James Howe.
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--| @copyright      Copyright 2017 Richard James Howe.
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--| @license        MIT
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--| @email          howe.r.j.89@gmail.com
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--|
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--| The control register contains both the value to compare the timer against
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--| as well as three control bits. Given a "timer_length" value of eight the
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--| control bits are:
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--|
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--| Bit     Input Description
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--| 7       Clock enable
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--| 6       Timer reset
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--| 5       Interrupt enable
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--| 4 - 0   Timer compare value
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--|
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-------------------------------------------------------------------------------
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library ieee,work,std;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity timer is
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	generic(
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		timer_length: positive := 16);
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	port(
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		clk:          in  std_ulogic;
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		rst:          in  std_ulogic;
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		we:           in  std_ulogic; -- write enable for control register
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		control_i:    in  std_ulogic_vector(timer_length - 1 downto 0); -- control register
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		counter_o:    out std_ulogic_vector(timer_length - 4 downto 0);
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		irq:          out std_ulogic); -- generate interrupt
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end entity;
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architecture behav of timer is
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	constant highest_bit:         positive := timer_length - 1;
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	constant control_enable_bit:  positive := highest_bit;
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	constant timer_reset_bit:     positive := highest_bit - 1;
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	constant irq_enable_bit:      positive := highest_bit - 2;
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	constant timer_highest_bit:   positive := highest_bit - 3;
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	signal control_c, control_n:  std_ulogic_vector(highest_bit downto 0) := (others => '0');
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	signal reset_timer:           std_ulogic  := '0';
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	signal enabled:               std_ulogic  := '0';
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	signal irq_en:                std_ulogic  := '0';
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	signal timer_reset:           std_ulogic  := '0';
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	signal compare:               std_ulogic_vector(timer_highest_bit downto 0) := (others => '0');
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	signal count:                 unsigned(timer_highest_bit downto 0)         := (others => '0');
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begin
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	assert (timer_length >= 4) report "Timer needs to be at least 4 bits wide: 3 bits for control - 1 for counter" severity failure;
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	enabled     <= control_c(control_enable_bit);
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	reset_timer <= control_c(timer_reset_bit);
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	irq_en      <= control_c(irq_enable_bit);
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	compare     <= control_c(timer_highest_bit downto 0);
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	counter_o   <= std_ulogic_vector(count);
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	clockRegisters: process(clk, rst)
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	begin
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		if rst = '1' then
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			control_c <= (others => '0');
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		elsif rising_edge(clk) then
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			control_c <= control_n;
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		end if;
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	end process;
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	counter: process (clk, rst)
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	begin
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		if rst = '1' then
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			count <= (others => '0');
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		elsif rising_edge(clk) then
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			if reset_timer = '1' or timer_reset = '1' then
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				count <= (others => '0');
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			elsif enabled = '1' then
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				count <= count + 1;
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			else
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				count <= count;
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			end if;
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		end if;
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	end process;
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	output: process(count, we, control_i, control_c, compare, irq_en, enabled)
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	begin
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		irq         <= '0';
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		control_n   <= control_c;
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		timer_reset <= '0';
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		control_n(timer_reset_bit)  <= '0'; -- reset
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		if we = '1' then
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			control_n <= control_i;
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		end if;
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		if count = unsigned(compare) and enabled = '1' then
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			if irq_en = '1' then
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				irq <= '1';
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			end if;
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			timer_reset <= '1';
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		end if;
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	end process;
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end architecture;
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