Project

General

Profile

Download (12.5 KB) Statistics
| Branch: | Tag: | Revision:
1
-------------------------------------------------------------------------------
2
--| @file h2.vhd
3
--| @brief The H2 Processor: J1 processor translation and extension.
4
--| Moved bit 12 to bit 4 to allow for more ALU instructions.
5
--|
6
--| @author         Richard James Howe.
7
--| @copyright      Copyright 2017 Richard James Howe.
8
--| @license        MIT
9
--| @email          howe.r.j.89@gmail.com
10
--|
11
-------------------------------------------------------------------------------
12

    
13
library ieee,work,std;
14
use ieee.std_logic_1164.all;
15
use ieee.numeric_std.all;
16

    
17
package h2_pkg is
18
	subtype word    is std_ulogic_vector(15 downto 0);
19
	subtype address is std_ulogic_vector(12 downto 0);
20

    
21
	constant hardware_cpu_id: word   := X"CAFE";
22
	constant simulation_cpu_id: word := X"DEAD";
23

    
24
	component h2 is
25
		generic(
26
			cpu_id:                   word     := hardware_cpu_id; -- Value for the CPU ID instruction
27
			interrupt_address_length: positive := 3;               -- Log_2 of the number of interrupts
28
			start_address:            natural  := 0;               -- Initial program counter value
29
			stack_size_log2:          positive := 6;               -- Log_2 of the Size of the stack
30
			use_interrupts:           boolean  := true);           -- Enable Interrupts in the H2 Core
31
		port(
32
			clk:      in  std_ulogic;
33
			rst:      in  std_ulogic;
34

    
35
			-- IO interface
36
			stop:     in  std_ulogic; -- Assert high to halt the H2 core
37

    
38
			io_wr:    out std_ulogic; -- Output Write Enable
39
			io_re:    out std_ulogic; -- Input  Read  Enable
40
			io_din:   in  word;      -- Data  Input from register
41
			io_dout:  out word;      -- Data  Output to register
42
			io_daddr: out word;      -- Data  Address for I/O action
43

    
44
			irq:      in  std_ulogic; -- Interrupt Request
45
			irq_addr: in  std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
46

    
47
			-- RAM interface, Dual port
48
			pc:       out address;   -- program counter
49
			insn:     in  word;      -- instruction
50

    
51
			dwe:      out std_ulogic; -- RAM data write enable
52
			dre:      out std_ulogic; -- RAM data read enable
53
			din:      in  word;       -- RAM data input
54
			dout:     out word;       -- RAM data output
55
			daddr:    out address);   -- RAM address
56
	end component;
57
end;
58

    
59
library ieee,work,std;
60
use ieee.std_logic_1164.all;
61
use ieee.numeric_std.all;
62
use ieee.math_real.all; -- only needed for calculations relating to generics
63
use work.h2_pkg.all;
64

    
65
entity h2 is
66
	generic(
67
		cpu_id:                   word     := hardware_cpu_id; -- Value for the CPU ID instruction
68
		interrupt_address_length: positive := 3;               -- Log_2 of the number of interrupts
69
		start_address:            natural  := 0;               -- Initial program counter value
70
		stack_size_log2:          positive := 6;               -- Log_2 of the Size of the stack
71
		use_interrupts:           boolean  := true);           -- Enable Interrupts in the H2 Core
72
	port(
73
		clk:      in  std_ulogic;
74
		rst:      in  std_ulogic;
75

    
76
		-- IO interface
77
		stop:     in  std_ulogic; -- Assert high to halt the H2 core
78

    
79
		io_wr:    out std_ulogic; -- Output Write Enable
80
		io_re:    out std_ulogic; -- Input  Read  Enable
81
		io_din:   in  word;       -- Data  Input from register
82
		io_dout:  out word;       -- Data  Output to register
83
		io_daddr: out word;       -- Data  Address for I/O action
84

    
85
		irq:      in  std_ulogic; -- Interrupt Request
86
		irq_addr: in  std_ulogic_vector(interrupt_address_length - 1 downto 0); -- Address to jump to on Interrupt Request
87

    
88
		-- RAM interface, Dual port
89
		pc:       out address;    -- program counter
90
		insn:     in  word;       -- instruction
91

    
92
		dwe:      out std_ulogic; -- RAM data write enable
93
		dre:      out std_ulogic; -- RAM data read enable
94
		din:      in  word;       -- RAM data input
95
		dout:     out word;       -- RAM data output
96
		daddr:    out address);   -- RAM address
97
end;
98

    
99
architecture rtl of h2 is
100

    
101
	signal pc_c:        address := std_ulogic_vector(to_unsigned(start_address, address'length));
102
	signal pc_n:        address := (others => '0');
103
	signal pc_plus_one: address := (others => '0');
104

    
105
	constant stack_size: integer := 2 ** stack_size_log2;
106
	type     stack_type is array (stack_size - 1 downto 0) of word;
107
	subtype  depth is unsigned(stack_size_log2 - 1 downto 0);
108

    
109
	signal vstkp_c, vstkp_n:  depth := (others => '0');             -- variable stack pointer
110
	signal vstk_ram: stack_type     := (others => (others => '0')); -- variable stack
111
	signal dstk_we: std_ulogic      := '0';                         -- variable stack write enable
112
	signal dd: depth                := (others => '0');             -- variable stack delta
113

    
114
	signal rstkp_c, rstkp_n:  depth := (others => '0');             -- return stack pointer
115
	signal rstk_ram: stack_type     := (others => (others => '0')); -- return stack
116
	signal rstk_we: std_ulogic      := '0';                         -- return stack write enable
117
	signal rd: depth                := (others => '0');             -- return stack delta
118

    
119
	type instruction_info_type is record
120
		alu:     std_ulogic;
121
		lit:     std_ulogic;
122
		branch:  std_ulogic;
123
		branch0: std_ulogic;
124
		call:    std_ulogic;
125
	end record;
126

    
127
	signal is_instr: instruction_info_type := ('0', '0', '0', '0', '0');
128

    
129
	signal is_interrupt: std_ulogic := '0';
130
	signal is_ram_write: std_ulogic := '0';
131

    
132
	type compare_type is record
133
		more:  std_ulogic;
134
		equal: std_ulogic;
135
		umore: std_ulogic;
136
		zero:  std_ulogic;
137
	end record;
138

    
139
	signal compare: compare_type := ('0', '0', '0', '0');
140

    
141
	signal int_en_c, int_en_n:     std_ulogic :=  '0'; -- interrupt enable
142
	signal irq_c, irq_n:           std_ulogic :=  '0'; -- interrupt request
143
	signal irq_addr_c, irq_addr_n: std_ulogic_vector(irq_addr'range) :=  (others => '0');
144

    
145
	signal tos_c, tos_n: word := (others => '0'); -- top of stack
146
	signal nos:          word := (others => '0'); -- next on stack
147
	signal rtos_c:       word := (others => '0'); -- top of return stack
148
	signal rstk_data:    word := (others => '0'); -- return stack input
149
	signal aluop:        std_ulogic_vector(4 downto 0) := (others => '0'); -- ALU operation
150

    
151
begin
152
	assert stack_size > 4 report "stack size too small: " & integer'image(stack_size) severity failure;
153

    
154
	is_instr.alu     <= '1' when insn(15 downto 13) = "011" else '0';
155
	is_instr.lit     <= '1' when insn(15)           = '1'   else '0';
156
	is_instr.branch  <= '1' when insn(15 downto 13) = "000" else '0';
157
	is_instr.branch0 <= '1' when insn(15 downto 13) = "001" else '0';
158
	is_instr.call    <= '1' when insn(15 downto 13) = "010" else '0';
159
	is_interrupt     <= '1' when irq_c = '1' and int_en_c = '1' and use_interrupts else '0';
160
	is_ram_write     <= '1' when is_interrupt = '0' and is_instr.alu = '1' and insn(5) = '1' else '0';
161
	compare.more     <= '1' when signed(tos_c)   > signed(nos)   else '0';
162
	compare.umore    <= '1' when unsigned(tos_c) > unsigned(nos) else '0';
163
	compare.equal    <= '1' when tos_c = nos else '0';
164
	compare.zero     <= '1' when unsigned(tos_c(15 downto 0)) = 0 else '0';
165
	nos              <= vstk_ram(to_integer(vstkp_c));
166
	rtos_c           <= rstk_ram(to_integer(rstkp_c));
167
	pc               <= pc_n;
168
	pc_plus_one      <= std_ulogic_vector(unsigned(pc_c) + 1);
169
	dout             <= nos;
170
	daddr            <= tos_c(13 downto 1) when is_ram_write = '1' else tos_n(13 downto 1);
171
	dwe              <= '1' when is_ram_write = '1' and tos_c(15 downto 14) = "00" else '0';
172
	dre              <= '1' when tos_n(15 downto 14) = "00" else '0';
173
	io_dout          <= nos;
174
	io_daddr         <= tos_c;
175
	io_wr            <= '1' when is_ram_write = '1' and tos_c(15 downto 14) /= "00" else '0';
176
	dd               <= (0 => insn(0), others => insn(1)); -- sign extend
177
	rd               <= (0 => insn(2), others => insn(3)); -- sign extend
178
	dstk_we          <= '1' when is_interrupt = '0' and (is_instr.lit = '1' or (is_instr.alu = '1' and insn(7) = '1')) else '0';
179

    
180
	next_state: process(clk, rst)
181
	begin
182
		if rst = '1' then
183
			vstkp_c    <= (others => '0');
184
			rstkp_c    <= (others => '0');
185
			pc_c       <= std_ulogic_vector(to_unsigned(start_address, pc_c'length));
186
			tos_c      <= (others => '0');
187
			int_en_c   <= '0';
188
			irq_c      <= '0';
189
			irq_addr_c <= (others => '0');
190
		elsif rising_edge(clk) then
191
			vstkp_c    <= vstkp_n;
192
			rstkp_c    <= rstkp_n;
193
			pc_c       <= pc_n;
194
			tos_c      <= tos_n;
195
			int_en_c   <= int_en_n;
196
			irq_c      <= irq_n;
197
			irq_addr_c <= irq_addr_n;
198
		end if;
199
	end process;
200

    
201
	stack_write: process(clk)
202
	begin
203
		if rising_edge(clk) then
204
			if dstk_we = '1' then
205
				vstk_ram(to_integer(vstkp_n)) <= tos_c;
206
			end if;
207
			if rstk_we = '1' then
208
				rstk_ram(to_integer(rstkp_n)) <= rstk_data;
209
			end if;
210
		end if;
211
	end process;
212

    
213
	alu_select: process(insn, is_instr, is_interrupt)
214
	begin
215
		if is_interrupt = '1' or is_instr.call = '1' or is_instr.branch = '1' then
216
			aluop <= (others => '0');
217
		elsif is_instr.branch0 = '1' then
218
			aluop <= (0 => '1', others => '0');
219
		elsif is_instr.alu = '1' then
220
			aluop <= insn(12 downto 8);
221
		else
222
			aluop <= (others => '0');
223
		end if;
224
	end process;
225

    
226
	alu: process(
227
		is_instr.lit,
228
		tos_c, nos, rtos_c,
229
		din, insn, aluop,
230
		io_din,
231
		vstkp_c, rstkp_c,
232
		compare,
233
		int_en_c,
234
		stop)
235
	begin
236
		io_re    <=  '0';      -- hardware reads can have side effects
237
		tos_n    <=  tos_c;
238
		int_en_n <=  int_en_c;
239
	if stop = '1' then
240
		null;
241
	elsif is_instr.lit = '1' then
242
		tos_n   <=  "0" & insn(14 downto 0);
243
	else
244
		case aluop is
245
		when "00000" => tos_n <= tos_c;
246
		when "00001" => tos_n <= nos;
247
		when "01011" => tos_n <= rtos_c;
248
		when "10100" => tos_n <= cpu_id;
249

    
250
		when "00011" => tos_n <= tos_c and nos;
251
		when "00100" => tos_n <= tos_c or nos;
252
		when "00101" => tos_n <= tos_c xor nos;
253
		when "00110" => tos_n <= not tos_c;
254

    
255
		when "00111" => tos_n <= (others => compare.equal);
256
		when "01000" => tos_n <= (others => compare.more);
257
		when "01111" => tos_n <= (others => compare.umore);
258
		when "10011" => tos_n <= (others => compare.zero);
259

    
260
		when "01001" => tos_n <= word(unsigned(nos) srl to_integer(unsigned(tos_c(3 downto 0))));
261
		when "01101" => tos_n <= word(unsigned(nos) sll to_integer(unsigned(tos_c(3 downto 0))));
262
		when "00010" => tos_n <= word(unsigned(nos) + unsigned(tos_c));
263
		when "01010" => tos_n <= word(unsigned(tos_c) - 1);
264

    
265
		when "01100" =>
266
			-- input: 0x4000 - 0x7FFF is external input
267
			if tos_c(15 downto 14) /= "00" then
268
				tos_n <= io_din;
269
				io_re <= '1';
270
			else
271
				tos_n <= din;
272
			end if;
273
		when "01110" => tos_n <= (others => '0');
274
				tos_n(vstkp_c'range) <= std_ulogic_vector(vstkp_c);
275
		when "10010" => tos_n <= (others => '0');
276
				tos_n(rstkp_c'range) <= std_ulogic_vector(rstkp_c);
277

    
278
		when "10001" => tos_n    <= (others => int_en_c);
279
		when "10000" => int_en_n <= tos_c(0);
280

    
281
		when others  => tos_n <= tos_c;
282
				report "Invalid ALU operation: " & integer'image(to_integer(unsigned(aluop))) severity error;
283
		end case;
284
	end if;
285
	end process;
286

    
287
	stack_update: process(
288
		pc_c, insn, tos_c,
289
		vstkp_c, dd,
290
		rstkp_c, rd,
291
		is_instr, is_interrupt, pc_plus_one, stop)
292
	begin
293
		vstkp_n   <= vstkp_c;
294
		rstkp_n   <= rstkp_c;
295
		rstk_we   <= '0';
296
		rstk_data <= "00" & pc_plus_one & "0";
297

    
298
		if stop = '1' then -- Do nothing
299
			null;
300
		elsif is_interrupt = '1' then -- Interrupts are similar to a call
301
			rstkp_n   <= rstkp_c + 1;
302
			rstk_we   <= '1';
303
			rstk_data <= "00" & pc_c & "0";
304
		elsif is_instr.lit = '1' then
305
			assert to_integer(vstkp_c) + 1 < stack_size;
306
			vstkp_n   <= vstkp_c + 1;
307
		elsif is_instr.alu = '1' then
308
			assert (not insn(6) = '1') or ((to_integer(rstkp_c) + to_integer(signed(rd))) < stack_size);
309
			assert                        ((to_integer(vstkp_c) + to_integer(signed(dd))) < stack_size);
310
			rstk_we   <= insn(6);
311
			rstk_data <= tos_c;
312
			vstkp_n   <= vstkp_c + unsigned(dd);
313
			rstkp_n   <= rstkp_c + unsigned(rd);
314
		elsif is_instr.branch0 = '1' then
315
			vstkp_n   <= vstkp_c - 1;
316
		elsif is_instr.call = '1' then
317
			rstkp_n   <= rstkp_c + 1;
318
			rstk_we   <= '1';
319
		end if;
320
	end process;
321

    
322
	pc_update: process(
323
		pc_c,insn, rtos_c, pc_plus_one,
324
		is_instr,
325
		is_interrupt, irq_c, irq_addr_c, irq_addr,irq,
326
		compare.zero,
327
		stop)
328
	begin
329
		pc_n       <= pc_c;
330
		irq_n      <= irq_c;
331
		irq_addr_n <= irq_addr_c;
332
		irq_n      <= irq;
333

    
334
		if irq = '1' then irq_addr_n <= irq_addr; end if;
335

    
336
		if stop = '1' then
337
			null;
338
		elsif is_interrupt = '1' then -- Update PC on interrupt
339
			irq_n      <= '0';
340
			irq_addr_n <= (others => '0');
341
			pc_n       <= (others => '0');
342
			pc_n(irq_addr'range) <= irq_addr_c;
343
		else -- Update PC on normal operations
344
			pc_n <=  pc_plus_one;
345
			if is_instr.branch = '1' or (is_instr.branch0 = '1' and compare.zero = '1') or is_instr.call = '1' then
346
				pc_n <=  insn(12 downto 0);
347
			elsif is_instr.alu = '1' and insn(4) = '1' then
348
				pc_n <=  rtos_c(13 downto 1);
349
			end if;
350
		end if;
351
	end process;
352
end architecture;
353

    
(1-1/4)