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library IEEE;
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use IEEE.std_logic_1164.ALL;
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entity failed_registers is
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   port
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   (
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      i_clock: in std_logic;
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      i_reset: in std_logic;
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      i_a:     in std_logic;
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      i_b:     in std_logic;
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      i_c:     in std_logic;
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      o_a:     out std_logic;
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      o_b:     out std_logic;
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      o_c:     out std_logic
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   );
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end entity failed_registers;
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architecture Behavioral of failed_registers is
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   signal flipflop_0: std_logic;
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   signal latch_0: std_logic;
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   signal latch_1: std_logic;
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begin
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   -- (not (is_simple_register_of flipflop_0 i_a i_clock))
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   -- (not (is_async_register_of flipflop_0 i_a i_clock))
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   -- (not (is_sync_register_of flipflop_0 i_a i_clock))
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   -- This is still a flipflop, but not one that simply stores 'i_a', instead
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   -- it seems to have an "enable" signal (i_c = '1').
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   process (i_clock)
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   begin
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      o_a <= i_a;
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      if (i_b = '1')
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      begin
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         o_b <= (not i_a);
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         if (rising_edge(i_clock))
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         begin
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            o_c <= flipflop_0;
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            if (i_c = '1')
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            then
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               flipflop_0 <= i_a;
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            end if;
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         end if;
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      else
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         if (rising_edge(i_clock))
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         begin
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            o_c <= (not flipflop_0);
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            flipflop_0 <= i_a;
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         end if;
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      end if;
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   end process;
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   -- (not (is_simple_register_of latch_0 i_a i_clock))
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   -- (not (is_async_register_of latch_0 i_a i_clock))
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   -- (not (is_sync_register_of latch_0 i_a i_clock))
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   -- This is not a flipflop: the last instruction actually overrides all
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   -- previous "assignements" to 'latch_0', meaning that 'latch_0' is
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   -- reassigned at every change in 'i_clock'.
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   process (i_clock)
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   begin
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      o_a <= i_a;
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      if (i_b = '1')
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      begin
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         o_b <= (not i_a);
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         if (rising_edge(i_clock))
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         begin
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            o_c <= latch_0;
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            if (i_c = '1')
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            then
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               latch_0 <= i_a;
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            else
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               latch_0 <= i_a;
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            end if;
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         end if;
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      else
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         if (rising_edge(i_clock))
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         begin
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            o_c <= (not latch_0);
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            latch_0 <= i_a;
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         end if;
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      end if;
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      latch_0 <= i_a;
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   end process;
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   -- (not (is_simple_register_of latch_1 i_a i_clock))
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   -- (not (is_async_register_of latch_1 i_a i_clock))
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   -- (not (is_sync_register_of latch_1 i_a i_clock))
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   -- This is not a flipflop: rising_edge in one branch, falling_edge in the
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   -- other.
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   process (i_clock)
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   begin
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      o_a <= i_a;
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      if (i_b = '1')
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      begin
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         o_b <= (not i_a);
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         if (rising_edge(i_clock))
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         begin
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            o_c <= latch_1;
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            if (i_c = '1')
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            then
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               latch_1 <= i_a;
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            else
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               latch_1 <= i_a;
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            end if;
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         end if;
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      else
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         if (falling_edge(i_clock))
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         begin
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            o_c <= (not flip_flop_6);
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            latch_1 <= i_a;
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         end if;
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      end if;
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   end process;
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end architecture;
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