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-- Company   : CNES
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-- Author    : Mickael Carl (CNES)
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-- Copyright : Copyright (c) CNES. 
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-- Licensing : GNU GPLv3
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-- Version         : V1
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-- Version history : 
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--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
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-- File name          : CNE_01000_good.vhd
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-- File Creation date : 2015-04-14
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-- Project name       : VHDL Handbook CNES Edition 
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-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
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-- Description : Handbook example: Identification of variable name: good example
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--
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-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
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--               demonstrating good practices in VHDL and as such, its design is minimalistic.
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--               It is provided as is, without any warranty.
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--               This example is compliant with the Handbook version 1.
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--
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-------------------------------------------------------------------------------------------------
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-- Naming conventions: 
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--
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-- i_Port: Input entity port
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-- o_Port: Output entity port
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-- b_Port: Bidirectional entity port
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-- g_My_Generic: Generic entity port
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--
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-- c_My_Constant: Constant definition 
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-- t_My_Type: Custom type definition
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--
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-- My_Signal_n: Active low signal
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-- v_My_Variable: Variable
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-- sm_My_Signal: FSM signal
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-- pkg_Param: Element Param coming from a package
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--
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-- My_Signal_re: Rising edge detection of My_Signal
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-- My_Signal_fe: Falling edge detection of My_Signal
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-- My_Signal_rX: X times registered My_Signal signal
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--
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-- P_Process_Name: Process
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--
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-------------------------------------------------------------------------------------------------
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity CNE_01000_good is
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   generic (
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      g_Width     : positive := 4                              -- Data Width
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   );
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   port  (
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      i_Clock     : in std_logic;                              -- Clock signal
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      i_Reset_n   : in std_logic;                              -- Reset signal
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      i_Data      : in std_logic_vector(g_Width-1 downto 0);   -- Data from which to count ones
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      o_Nb_One    : out std_logic_vector(g_Width-1 downto 0)   -- Number of ones in i_Data signal
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   );
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end CNE_01000_good;
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architecture Behavioral of CNE_01000_good is
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   -- Function to get the number of ones in a signal
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   function Get_Ones(data : in std_logic_vector(g_Width-1 downto 0)) return integer is
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      -- Number of ones in the input signal
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      variable v_Nb_Ones : integer range 0 to g_Width;
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   begin
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      v_Nb_Ones := 0;
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      -- Loop on each signal's bit
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      for i in 0 to g_Width-1 loop
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         if (data(i)='1') then
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            v_Nb_Ones := v_Nb_Ones + 1;
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         end if;
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      end loop;
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      return v_Nb_Ones;
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   end function;
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   -- Module output
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   signal Nb_One : std_logic_vector(g_Width-1 downto 0);
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begin
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   -- Counts the number of ones in a signal and register this count.
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   p_Count_Ones:process(i_Reset_n,i_Clock)
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   begin
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      if (i_Reset_n='0') then
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         Nb_One <= (others => '0');
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      elsif (rising_edge(i_Clock)) then
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            Nb_One <= std_logic_vector(to_unsigned(Get_Ones(i_Data),Nb_One'length));
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      end if;
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   end process;
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   o_Nb_One <= Nb_One;
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end Behavioral;
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