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Revision d93979b7

Added by Arnaud Dieumegard about 3 years ago

Update of vhdl samples files

View differences:

vhdl_json/vhdl_files/cnes_guidelines/cfg/user_handler.vhd
1
library IEEE;
2

  
3
use IEEE.std_logic_1164.all;
4

  
5
entity user_handler is
6
   port
7
   (
8
      i_clock:             in std_logic;  -- System's clock.
9
      i_reset:             in std_logic;  -- System reset.
10
      i_synced_start_btn:  in std_logic;  -- User input. Synchronized.
11
      i_synced_raz_btn:    in std_logic;  -- User input. Synchronized.
12
      i_limit_reached:     in std_logic;  -- Time Wizard has reached limit.
13
      o_enable:            out std_logic; -- Enable time passing.
14
      o_raz:               out std_logic  -- Reset system.
15
   );
16
end user_handler;
17

  
18
architecture Behavioral of user_handler is
19
   -- Previous value of BP_START_STOP (Lustre inspired).
20
   signal synced_start_btn_r1: std_logic;
21
   -- Remember if we are currently counting time or not.
22
   signal time_is_passing: std_logic;
23
begin
24
   P_ENABLE_TIME: process (i_clock, i_reset)
25
   begin
26
      if (i_reset = '1')
27
      then
28
         time_is_passing <= '0';
29
      else
30
         if (rising_edge(i_clock))
31
         then
32
            if ((synced_start_btn_r1 = '0') and (i_synced_start_btn = '1'))
33
            then
34
               time_is_passing <= (not time_is_passing);
35
            end if;
36
         end if;
37
      end if;
38
   end process;
39

  
40
   P_PRE_SYNCED_START_BTN: process (i_clock, i_reset)
41
   begin
42
      if (i_reset = '1')
43
      then
44
         synced_start_btn_r1 <= '0';
45
      else
46
         if (rising_edge(i_clock))
47
         then
48
            synced_start_btn_r1 <= i_synced_start_btn;
49
         end if;
50
      end if;
51
   end process;
52

  
53
   o_raz <= (i_synced_raz_btn and time_is_passing);
54
   o_enable <= time_is_passing;
55
end;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_00100_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-09 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_00100_good.vhd
12
-- File Creation date : 2015-04-09
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of active low signal: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_00100_good is
53
   port  (
54
      i_Clock     : in std_logic;   -- Clock signal
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_D         : in std_logic;   -- D Flip-Flop input signal
57
      o_Q         : out std_logic   -- D Flip-Flop output signal
58
   );
59
end CNE_00100_good;
60

  
61
architecture Behavioral of CNE_00100_good is
62
   signal Q   : std_logic; -- D Flip-Flop output
63
begin
64
   --CODE
65
   -- D FlipFlop process
66
   P_FlipFlop:process(i_Clock, i_Reset_n)
67
   begin
68
      if (i_Reset_n='0') then
69
         Q <= '0';
70
      elsif (rising_edge(i_Clock)) then
71
            Q <= i_D;
72
      end if;
73
   end process;
74
   --CODE
75
   
76
   o_Q <= Q;
77
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_00200_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-09 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_00200_good.vhd
12
-- File Creation date : 2015-04-09
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Unsuitability of frequency in clock name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_00200_good is
54
   port  (
55
      i_Clock_div2   : in std_logic;   -- Clock signal
56
      i_Reset_n      : in std_logic;   -- Reset signal
57
      i_D            : in std_logic;   -- D Flip-Flop input signal
58
      o_Q            : out std_logic   -- D Flip-Flop output signal
59
   );
60
end CNE_00200_good;
61
--CODE
62

  
63
architecture Behavioral of CNE_00200_good is
64
   signal Q   : std_logic; -- D Flip-Flop output
65
begin
66
   -- D FlipFlop process
67
   P_FlipFlop:process(i_Clock_div2, i_Reset_n)
68
   begin
69
      if (i_Reset_n='0') then
70
         Q <= '0';
71
      elsif (rising_edge(i_Clock_div2)) then
72
            Q <= i_D;
73
      end if;
74
   end process;
75
   
76
   o_Q <= Q;
77
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_00300_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-09 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_00300_good.vhd
12
-- File Creation date : 2015-04-09
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Unsuitability of pin number in signal name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_00300_good is
54
   port  (
55
      i_Clock     : in std_logic;   -- Clock signal
56
      i_Reset_n   : in std_logic;   -- Reset signal
57
      i_D         : in std_logic;   -- D Flip-Flop input signal
58
      o_Q         : out std_logic   -- D Flip-Flop output signal
59
   );
60
end CNE_00300_good;
61
--CODE
62

  
63
architecture Behavioral of CNE_00300_good is
64
   signal Q : std_logic;   -- Internal signal to work with
65
begin
66
   -- D FlipFlop process
67
   P_FlipFlop:process(i_Clock, i_Reset_n)
68
   begin
69
      if (i_Reset_n='0') then
70
         Q <= '0';
71
      elsif (rising_edge(i_Clock)) then
72
            Q <= i_D;
73
      end if;
74
   end process;
75
   
76
   o_Q <= Q;
77
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01000_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01000_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of variable name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_01000_good is
53
   generic (
54
      g_Width     : positive := 4                              -- Data Width
55
   );
56
   port  (
57
      i_Clock     : in std_logic;                              -- Clock signal
58
      i_Reset_n   : in std_logic;                              -- Reset signal
59
      i_Data      : in std_logic_vector(g_Width-1 downto 0);   -- Data from which to count ones
60
      o_Nb_One    : out std_logic_vector(g_Width-1 downto 0)   -- Number of ones in i_Data signal
61
   );
62
end CNE_01000_good;
63

  
64
architecture Behavioral of CNE_01000_good is
65
   -- Function to get the number of ones in a signal
66
   function Get_Ones(data : in std_logic_vector(g_Width-1 downto 0)) return integer is
67
      -- Number of ones in the input signal
68
      variable v_Nb_Ones : integer range 0 to g_Width;
69
   begin
70
      v_Nb_Ones := 0;
71
      -- Loop on each signal's bit
72
      for i in 0 to g_Width-1 loop
73
         if (data(i)='1') then
74
            v_Nb_Ones := v_Nb_Ones + 1;
75
         end if;
76
      end loop;
77
      return v_Nb_Ones;
78
   end function;
79
   
80
   -- Module output
81
   signal Nb_One : std_logic_vector(g_Width-1 downto 0);
82
begin
83
   -- Counts the number of ones in a signal and register this count.
84
   p_Count_Ones:process(i_Reset_n,i_Clock)
85
   begin
86
      if (i_Reset_n='0') then
87
         Nb_One <= (others => '0');
88
      elsif (rising_edge(i_Clock)) then
89
            Nb_One <= std_logic_vector(to_unsigned(Get_Ones(i_Data),Nb_One'length));
90
      end if;
91
   end process;
92
   
93
   o_Nb_One <= Nb_One;
94
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01100_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01100_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of ports direction inside entity port name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_01100_good is
54
   port  (
55
      i_Clock     : in std_logic;   -- Clock signal
56
      i_Reset_n   : in std_logic;   -- Reset signal
57
      i_D         : in std_logic;   -- D Flip-Flop input signal
58
      o_Q         : out std_logic   -- D Flip-Flop output signal
59
   );
60
end CNE_01100_good;
61
--CODE
62

  
63
architecture Behavioral of CNE_01100_good is
64
   signal Q   : std_logic; -- D Flip-Flop output
65
begin
66
   -- D FlipFlop process
67
   P_FlipFlop:process(i_Clock, i_Reset_n)
68
   begin
69
      if (i_Reset_n='0') then
70
         Q <= '0';
71
      elsif (rising_edge(i_Clock)) then
72
            Q <= i_D;
73
      end if;
74
   end process;
75
   
76
   o_Q <= Q;
77
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01200_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01200_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of process label: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_01200_good is
53
   port  (
54
      i_Clock     : in std_logic;   -- Clock signal
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_D         : in std_logic;   -- D Flip-Flop input signal
57
      o_Q         : out std_logic   -- D Flip-Flop output signal
58
   );
59
end CNE_01200_good;
60

  
61
architecture Behavioral of CNE_01200_good is
62
   signal Q   : std_logic; -- D Flip-Flop output
63
begin
64
   --CODE
65
   -- D FlipFlop process
66
   P_FlipFlop:process(i_Clock, i_Reset_n)
67
   begin
68
      if (i_Reset_n='0') then
69
         Q <= '0';
70
      elsif (rising_edge(i_Clock)) then
71
            Q <= i_D;
72
      end if;
73
   end process;
74
   --CODE
75
   
76
   o_Q <= Q;
77
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01300_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01300_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of constant name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_01300_good is
53
   port (
54
      i_Clock     : in std_logic;                     -- Main clock signal
55
      i_Reset_n   : in std_logic;                     -- Main reset signal
56
      i_Enable    : in std_logic;                     -- Enables the counter
57
      o_Count     : out std_logic_vector(3 downto 0)  -- Counter (unsigned value)
58
   );
59
end CNE_01300_good;
60

  
61
architecture Behavioral of CNE_01300_good is
62
   signal Count  : unsigned(3 downto 0); -- Counter output signal (unsigned converted)
63
   constant c_Length : unsigned(3 downto 0) := "1001"; -- Counter period
64
begin
65
   -- Will count undefinitely from 0 to i_Length while i_Enable is asserted
66
   P_Count:process(i_Reset_n, i_Clock)
67
   begin
68
      if (i_Reset_n='0') then
69
         Count <= (others => '0');
70
      elsif (rising_edge(i_Clock)) then
71
            if (Count>=c_Length) then -- Counter restarts from 0
72
               Count <= (others => '0');
73
            elsif (i_Enable='1') then -- Increment counter value
74
               Count <= Count + 1;
75
            end if;
76
      end if;
77
   end process;
78

  
79
o_Count <= std_logic_vector(Count);
80

  
81
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01400_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01400_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of generic port name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_01400_good is
54
   generic (g_Width : positive := 3);
55
   port  (
56
      i_D0  : in std_logic_vector(g_Width downto 0); -- First Mux input
57
      i_D1  : in std_logic_vector(g_Width downto 0); -- Second Mux input
58
      i_Sel : in std_logic;                        -- Mux select input
59
      o_D   : out std_logic_vector(g_Width downto 0) -- Mux output
60
   );
61
end CNE_01400_good;
62
--CODE
63

  
64
architecture Behavioral of CNE_01400_good is
65
begin
66
   -- Simple Mux, output depends on select value
67
   o_D <= i_D1 when i_Sel='1'
68
     else i_D0;
69
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01500_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-15 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01500_good.vhd
12
-- File Creation date : 2015-04-15
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of custom type name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_01500_good is
53
port  (
54
      i_Reset_n   : in std_logic;                     -- Reset signal
55
      i_Clock     : in std_logic;                     -- Clock signal
56
      i_Addr      : in std_logic_vector(1 downto 0);  -- Address to read from or write to
57
      i_Rd        : in std_logic;                     -- Read signal
58
      i_Wr        : in std_logic;                     -- Write signal
59
      i_Data      : in std_logic;                     -- Incoming data to write
60
      o_Data      : out std_logic                     -- Data read
61
   );
62
end CNE_01500_good;
63

  
64
--CODE
65
architecture Behavioral of CNE_01500_good is
66
   type t_register is array (0 to 3) of std_logic; -- Array for signal registration
67
   signal D : t_register;                          -- Actual signal
68
   signal Data : std_logic;                        -- Module output
69
begin
70
   -- Describes a simple Register bank with Read and Write signals
71
   P_Register_Bank:process(i_Reset_n, i_Clock)
72
   begin
73
      if (i_Reset_n='0') then
74
         D <= (others => '0');
75
         Data <= '0';
76
      elsif (rising_edge(i_Clock)) then
77
            if (i_Rd='1') then
78
            -- Read memory
79
               Data <= D(to_integer(unsigned(i_Addr)));
80
            elsif (i_Wr='1') then
81
            -- Write memory
82
               D(to_integer(unsigned(i_Addr))) <= i_Data;
83
            end if;
84
      end if;
85
   end process;
86
   
87
   o_Data <= Data;
88
end Behavioral;
89
--CODE
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01600_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-15 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01600_good.vhd
12
-- File Creation date : 2015-04-15
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of package element: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
library work;
53
use work.pkg_HBK.all;
54

  
55
entity CNE_01600_good is
56
   port  (
57
      i_Clock     : in std_logic;                              -- Global clock signal
58
      i_Reset_n   : in std_logic;                              -- Global reset signal
59
      i_Raz       : in std_logic;                              -- Reset counting and load length
60
      i_Enable    : in std_logic;                              -- Enable the counter
61
      i_Length    : in std_logic_vector(pkg_Width downto 0);   -- How much the module should count (Value expected - 1)
62
      o_Done      : out std_logic                              -- Counter output
63
   );
64
end CNE_01600_good;
65

  
66
architecture Behavioral of CNE_01600_good is
67
   signal Count   : signed(pkg_Width downto 0); -- Counting signal
68
   signal Length  : signed(pkg_Width downto 0); -- How much the module should count
69
   signal Done    : std_logic;                  -- Counter output
70
begin
71
   P_Count:process(i_Reset_n, i_Clock)
72
   begin
73
      if (i_Reset_n='0') then
74
         Count <= (others => '0');
75
         Length <= (others => '0');
76
         Done <= '0';
77
      elsif (rising_edge(i_Clock)) then
78
            if (i_Raz='1') then
79
            -- Reset the counting
80
               Length <= signed(i_Length);
81
               Count <= (others => '0');
82
            elsif (i_Enable='1' and Done='0') then
83
            -- Counter activated and not finished
84
               Count <= Count + 1;
85
            end if;
86
            if (Count>=Length) then -- Compared elements are of the same type and dimension
87
            -- Counter finished
88
               Done <= '1';
89
            else
90
               Done <= '0';
91
            end if;
92
      end if;
93
   end process;
94
   
95
   o_Done <= Done;
96
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01700_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01700_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of rising edge detection signal: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_01700_good is
54
   port  (
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_Clock     : in std_logic;   -- Clock signal
57
      i_D         : in std_logic;   -- Signal on which detect edges
58
      o_D_re      : out std_logic   -- Rising edge of i_D
59
   );
60
end CNE_01700_good;
61

  
62
architecture Behavioral of CNE_01700_good is
63
   signal D_r1 : std_logic; -- i_D registered 1 time
64
   signal D_r2 : std_logic; -- i_D registered 2 times
65
begin
66
   -- Rising edge detection process
67
   P_detection: process(i_Reset_n, i_Clock)
68
   begin
69
      if (i_Reset_n='0') then
70
         D_r1 <= '0';
71
         D_r2 <= '0';
72
      elsif (rising_edge(i_Clock)) then
73
            D_r1 <= i_D;
74
            D_r2 <= D_r1;
75
      end if;
76
   end process;
77
   
78
   o_D_re <= D_r1 and not D_r2;
79
end Behavioral;
80
--CODE
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01800_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01800_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of falling edge detection signal: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_01800_good is
54
   port  (
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_Clock     : in std_logic;   -- Clock signal
57
      i_D         : in std_logic;   -- Signal on which detect edges
58
      o_D_fe      : out std_logic   -- Falling edge of i_D
59
   );
60
end CNE_01800_good;
61

  
62
architecture Behavioral of CNE_01800_good is
63
   signal D_r1  : std_logic; -- i_D registered 1 time
64
   signal D_r2  : std_logic; -- i_D registered 2 times
65
begin
66
   -- Rising edge detection process
67
   P_detection: process(i_Reset_n, i_Clock)
68
   begin
69
      if (i_Reset_n='0') then
70
         D_r1 <= '0';
71
         D_r2 <= '0';
72
      elsif (rising_edge(i_Clock)) then
73
            D_r1 <= i_D;
74
            D_r2 <= D_r1;
75
      end if;
76
   end process;
77
   
78
   o_D_fe <= not D_r1 and D_r2;
79
end Behavioral;
80
--CODE
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_01900_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_01900_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of registered signals: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
--CODE
53
entity CNE_01900_good is
54
   port  (
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_Clock     : in std_logic;   -- Clock signal
57
      i_D    : in std_logic;   -- Signal on which detect edges
58
      o_D_re : out std_logic   -- Rising edge of My_Sig
59
   );
60
end CNE_01900_good;
61

  
62
architecture Behavioral of CNE_01900_good is
63
   signal D_r1  : std_logic; -- i_D registered 1 time
64
   signal D_r2  : std_logic; -- i_D registered 2 times
65
begin
66
   -- Rising edge detection process
67
   P_detection: process(i_Reset_n, i_Clock)
68
   begin
69
      if (i_Reset_n='0') then
70
         D_r1 <= '0';
71
         D_r2 <= '0';
72
      elsif (rising_edge(i_Clock)) then
73
            D_r1 <= i_D;
74
            D_r2 <= D_r1;
75
      end if;
76
   end process;
77
   
78
   o_D_re <= D_r1 and not D_r2;
79
end Behavioral;
80
--CODE
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_02000_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-20 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_02000_good.vhd
12
-- File Creation date : 2015-04-20
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Identification of Finite State Machine: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_02000_good is
53
   port  (
54
      i_Clock     : in std_logic;   -- Clock input
55
      i_Reset_n   : in std_logic;   -- Reset input
56
      i_Start     : in std_logic;   -- Start counter signal
57
      i_Stop      : in std_logic    -- Stop counter signal
58
   );
59
end CNE_02000_good;
60

  
61
architecture Behavioral of CNE_02000_good is
62
   constant c_Length : std_logic_vector(3 downto 0) := (others => '1'); -- How long we should count
63
--CODE
64
   type t_state      is (init, loading, enabled, finished);             -- Enumerated type for state encoding
65
   signal sm_State   : t_state;                                         -- State signal
66
--CODE
67
   signal Raz        : std_logic;                                       -- Load the length value and initialize the counter
68
   signal Enable     : std_logic;                                       -- Counter enable signal
69
   signal Length     : std_logic_vector(3 downto 0);                    -- Counter length for counting
70
   signal End_Count  : std_logic;                                       -- End signal of counter
71
begin
72
   -- A simple counter with loading length and enable signal
73
   Counter:Counter
74
   port map (
75
      i_Clock     => i_Clock,
76
      i_Reset_n   => i_Reset_n,
77
      i_Raz       => Raz,
78
      i_Enable    => Enable,
79
      i_Length    => Length,
80
      o_Done      => End_Count
81
   );
82
   
83
   -- FSM process controlling the counter. Start or stop it in function of the input (i_Start & i_Stop), 
84
   -- load the length value, and wait for it to finish
85
   P_FSM:process(i_Reset_n, i_Clock)
86
   begin
87
      if (i_Reset_n='0') then
88
         sm_State <= init;
89
      elsif (rising_edge(i_Clock)) then
90
            case sm_State is
91
               when init => 
92
               -- Set the length value
93
                  Length <= c_Length;
94
                  sm_State <= loading;
95
               when loading =>
96
               -- Load the counter and initialize it
97
                  Raz <= '1';
98
                  sm_State <= enabled;
99
               when enabled =>
100
               -- Start or stop counting depending on inputs until it finishes
101
                  Raz <= '0';
102
                  if (End_Count='0') then
103
                     Enable <= i_Start xor not i_Stop;
104
                     sm_State  <= Enabled;
105
                  else
106
                     Enable <= '0';
107
                     sm_State <= finished;
108
                  end if;
109
               when others =>
110
                  sm_State <= init;
111
            end case;
112
      end if;
113
   end process;
114
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_02100_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-14 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_02100_good.vhd
12
-- File Creation date : 2015-04-14
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Name of RTL architecture: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
entity CNE_02100_good is
53
   port  (
54
      i_Clock     : in std_logic;   -- Clock signal
55
      i_Reset_n   : in std_logic;   -- Reset signal
56
      i_D         : in std_logic;   -- D Flip-Flop input signal
57
      o_Q         : out std_logic   -- D Flip-Flop output signal 
58
   );
59
end CNE_02100_good;
60

  
61
--CODE
62
architecture Behavioral of CNE_02100_good is
63
--CODE
64
   signal Q   : std_logic; -- D Flip-Flop output
65
begin
66
   -- D FlipFlop process
67
   P_FlipFlop:process(i_Clock, i_Reset_n)
68
   begin
69
      if (i_Reset_n='0') then
70
         Q <= '0';
71
      elsif (rising_edge(i_Clock)) then
72
            Q <= i_D;
73
      end if;
74
   end process;
75
   
76
   o_Q <= Q;
77
end Behavioral;
vhdl_json/vhdl_files/cnes_guidelines/rule/data/CNE_02300_good.vhd
1
-------------------------------------------------------------------------------------------------
2
-- Company   : CNES
3
-- Author    : Mickael Carl (CNES)
4
-- Copyright : Copyright (c) CNES. 
5
-- Licensing : GNU GPLv3
6
-------------------------------------------------------------------------------------------------
7
-- Version         : V1
8
-- Version history : 
9
--    V1 : 2015-04-15 : Mickael Carl (CNES): Creation
10
-------------------------------------------------------------------------------------------------
11
-- File name          : CNE_02300_good.vhd
12
-- File Creation date : 2015-04-15
13
-- Project name       : VHDL Handbook CNES Edition 
14
-------------------------------------------------------------------------------------------------
15
-- Softwares             :  Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
16
-------------------------------------------------------------------------------------------------
17
-- Description : Handbook example: Preservation of clock name: good example
18
--
19
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
20
--               demonstrating good practices in VHDL and as such, its design is minimalistic.
21
--               It is provided as is, without any warranty.
22
--               This example is compliant with the Handbook version 1.
23
--
24
-------------------------------------------------------------------------------------------------
25
-- Naming conventions: 
26
--
27
-- i_Port: Input entity port
28
-- o_Port: Output entity port
29
-- b_Port: Bidirectional entity port
30
-- g_My_Generic: Generic entity port
31
--
32
-- c_My_Constant: Constant definition 
33
-- t_My_Type: Custom type definition
34
--
35
-- My_Signal_n: Active low signal
36
-- v_My_Variable: Variable
37
-- sm_My_Signal: FSM signal
38
-- pkg_Param: Element Param coming from a package
39
--
40
-- My_Signal_re: Rising edge detection of My_Signal
41
-- My_Signal_fe: Falling edge detection of My_Signal
42
-- My_Signal_rX: X times registered My_Signal signal
43
--
44
-- P_Process_Name: Process
45
--
46
-------------------------------------------------------------------------------------------------
47

  
48
library IEEE;
49
use IEEE.std_logic_1164.all;
50
use IEEE.numeric_std.all;
51

  
52
library work;
53
use work.pkg_HBK.all;
54

  
55
--CODE
56
entity CNE_02300_good is
57
   port  (
58
      i_Clock     : in std_logic;   -- Clock signal
59
      i_Reset_n   : in std_logic;   -- Reset signal
60
      i_D         : in std_logic;   -- D Flip-Flop input signal
61
      o_Q         : out std_logic   -- D Flip-Flop output signal
62
   );
63
end CNE_02300_good;
64

  
65
architecture Behavioral of CNE_02300_good is
66
begin
67
   DFF1:DFlipFlop
68
   port map (
69
      i_Clock     => i_Clock,
70
      i_Reset_n   => i_Reset_n,
71
      i_D         => i_D,
72
      o_Q         => o_Q,
73
      o_Q_n       => open
74
   );
75
end Behavioral;
76
--CODE
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