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1 d93979b7 Arnaud Dieumegard
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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_17_ch_17_04.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_17_04 is
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end entity ch_17_04;
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----------------------------------------------------------------
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architecture test of ch_17_04 is
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begin
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  process is
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            -- code from book:
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            type stimulus_record is record
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                                      stimulus_time : time;
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                                      stimulus_value : bit_vector(0 to 3);
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                                    end record stimulus_record;
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          type stimulus_ptr is access stimulus_record;
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          variable bus_stimulus : stimulus_ptr;
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          -- end of code from book
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  begin
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    bus_stimulus := new stimulus_record;
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    bus_stimulus.all := stimulus_record'(20 ns, B"0011");
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    report time'image(bus_stimulus.all.stimulus_time);
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    report time'image(bus_stimulus.stimulus_time);
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    wait;
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  end process;
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end architecture test;