Project

General

Profile

Download (2.26 KB) Statistics
| Branch: | Tag: | Revision:
1 d93979b7 Arnaud Dieumegard
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4
-- This file is part of VESTs (Vhdl tESTs).
5
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_16_fg_16_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26
27
-- not in book
28
29
entity example_entity is
30
end entity example_entity;
31
32
-- end not in book
33
34
35
architecture contrived of example_entity is
36
37
  constant sig_width : positive := 16;
38
  signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
39
  signal sel : bit;
40
  -- . . .
41
42
begin
43
44
  mux : block is
45
                generic ( width : positive );
46
              generic map ( width => sig_width );
47
              port ( d0, d1 : in bit_vector(0 to width - 1);
48
                     y : out bit_vector(0 to width - 1);
49
                     sel : in bit);
50
              port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
51
52
              constant zero : bit_vector(0 to width - 1) := ( others => '0' );
53
              signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
54
55
  begin
56
    gated_d0 <= d0 when sel = '0' else zero;
57
    gated_d1 <= d1 when sel = '1' else zero;
58
    y <= gated_d0 or gated_d1;
59
  end block mux;
60
61
  -- . . .
62
63
  -- not in book
64
65
  stimulus : process is
66
  begin
67
    s1 <= X"1111";  s2 <= X"2222";  sel <= '0';  wait for 10 ns;
68
    s1 <= X"0101";  wait for 10 ns;
69
    s2 <= X"0202";  wait for 10 ns;
70
    sel <= '1';  wait for 10 ns;
71
    s1 <= X"0001";  wait for 10 ns;
72
    s2 <= X"0002";  wait for 10 ns;
73
74
    wait;
75
  end process stimulus;
76
77
  -- end not in book
78
79
end architecture contrived;