Project

General

Profile

Download (2.62 KB) Statistics
| Branch: | Tag: | Revision:
1 d93979b7 Arnaud Dieumegard
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3
4
-- This file is part of VESTs (Vhdl tESTs).
5
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_16_fg_16_10.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26
27
entity computer_system is
28
end entity computer_system;
29
30
31
-- code from book
32
33
architecture abstract of computer_system is
34
35
  -- not in book
36
37
  subtype word is bit_vector(31 downto 0);
38
  type word_vector is array (natural range <>) of word;
39
40
  function resolve_word ( drivers : word_vector ) return word is
41
  begin
42
    if drivers'length > 0 then
43
      return drivers(drivers'left);
44
    else
45
      return X"00000000";
46
    end if;
47
  end function resolve_word;
48
49
  -- end not in book
50
51
  -- . . .
52
53
  signal address_bus : resolve_word word bus;
54
  signal hold_req : bit;
55
  -- . . .
56
57
  -- not in book
58
  signal clk : bit := '0';
59
  -- end not in book
60
61
begin
62
63
  cpu : block is
64
65
                signal guard : boolean := false;
66
              signal cpu_internal_address : word;
67
              -- . . .
68
69
  begin
70
71
    cpu_address_driver:
72
      address_bus <= guarded cpu_internal_address;
73
74
    -- . . .    -- other bus drivers
75
76
    controller : process is
77
                           -- . . .
78
    begin
79
      -- . . .
80
      -- . . .    -- determine when to disable cpu bus drivers
81
      guard <= false;
82
      wait on clk until hold_req = '0' and clk = '1';
83
      guard <= true;  -- re-enable cpu bus drivers
84
      -- . . .
85
      -- not in book
86
      wait until clk = '1';
87
      -- end not in book
88
    end process controller;
89
90
    -- . . .    -- cpu datapath processes
91
92
    -- not in book
93
    cpu_internal_address <= X"11111111";
94
    -- end not in book
95
96
  end block cpu;
97
98
  -- . . .    -- blocks for DMA and other modules
99
100
  -- not in book
101
  clk <= '1' after 10 ns, '0' after 20 ns when clk = '0';
102
  -- end not in book
103
104
end architecture abstract;
105
106
-- end code from book